无法合成信号

Question

当谈到 VHDL 时，我是一个新手，但我正在使用一个计数器，而不是通过按一个按钮手动上下计数。不知何故，我只是得到这个错误，我不知道我在做什么错了，其他检查都很好。有什么建议吗？

这是我得到的错误：

ERROR:Xst:827 - 第 101 行：信号 s2 无法合成，同步描述错误。 当前软件版本不支持您用于描述同步元素（寄存器、内存等）的描述样式。

entity updown is Port (
    rst : in  STD_LOGIC;
    plus , plusin: in  STD_LOGIC;
    minus, minusin : in  STD_LOGIC;
    clk : in  STD_LOGIC;
    ud_out, ud_out2 : out  STD_LOGIC_VECTOR (3 downto 0)
);
end updown;

architecture Behavioral of updown is
    signal s  : unsigned (3 downto 0):= "0000";
    signal s2 : unsigned (3 downto 0) := "0000";
begin

    process(rst, plus, minus, clk, plusin, minusin)
    begin

        if rst='1' then
            s <= "0000";
            s2 <= "0000";
        else
            if rising_edge (clk) then 
                if plus ='1' or plusin = '1' then 
                    if s = "1001" then
                        s <= "0000";
                        if s2 = "1001" then 
                            s2 <= "0000";
                        else
                            s2 <= s2 + 1;
                        end if;                 
                    else
                        s <= s + 1;
                    end if;
                end if;
            else 
                if minus ='1' or minusin = '1' then 
                    if s = "0000" then
                        s <= "1001";

                        if s2= "0000" then
                            s2 <= "1001";
                        else 
                            s2 <= s2 - 1;
                        end if;
                    else 
                        s <= s - 1;
                    end if;             
                end if;
            end if;
        end if;

    end process;

    ud_out <= std_logic_vector(s);
    ud_out2 <= std_logic_vector(s2);

end Behavioral;

Answer 1

您对同步过程的描述有缺陷。同步进程的事件仅在时钟信号的边缘更新（尽管在这种情况下也有异步复位行为）

您的敏感度列表包含的内容超出了描述同步过程所需的内容。

替换

process(rst, plus, minus, clk, plusin, minusin)

与

process(rst, clk )

然后，信号将仅在时钟转换或 rst 更改时更新。

有些编译器更加挑剔，可能需要您更改

else if rising_edge (clk)then 

到

elsif rising_edge(clk) then 

编辑：

这应该可行。我已经清楚地列出了它，所以它实际上很容易理解正在发生的事情。我建议你以后也这样做。它使简单的关闭错误很容易被发现

entity updown is
port ( 
   signal clk     : in   std_logic;
   signal rst     : in   std_logic;
   signal plus    : in   std_logic;
   signal plusin  : in   std_logic;
   signal minus   : in   std_logic;
   signal minusin : in   std_logic;
   signal ud_out  : out  std_logic_vector(3 downto 0);
   signal ud_out2 : out  std_logic_vector(3 downto 0)
);
end entity updown;

architecture behavioral of updown is

    signal s  : unsigned (3 downto 0);
    signal s2 : unsigned (3 downto 0);

begin

   p_counter_process: process(rst, clk)
   begin

      if rst ='1' then 
         s  <= (others => '0');
         s2 <= (others => '0');

      elsif rising_edge(clk) then 

         if plus ='1' or plusin = '1' then 

            if s = "1001" then            
               s <= "0000";

               if s2 = "1001" then 
                  s2 <= "0000";
               else
                  s2 <= s2 + 1;
               end if;                 

            else
                s <= s +1;
            end if;
        end if;

        -- you had a mismatched end if statement here. Removed

        if minus ='1' or minusin = '1' then 

           if s = "0000" then 
              s <= "1001";

              if s2= "0000" then 
                 s2 <= "1001";
              else 
                 s2 <= s2 - 1;
              end if;
           else 
              s <= s - 1;
           end if;             
        end if;

      end if;
   end process;

   ud_out  <= std_logic_vector(s);
   ud_out2 <= std_logic_vector(s2);

end architecture;