信号 temp2 无法合成，同步描述错误

Question

entity timer is
    Port ( click : in  STD_LOGIC;
           clear : out  STD_LOGIC;
           t_unlock : out  STD_LOGIC);
end timer;

architecture Behavioral of timer is
    signal temp2 : integer range 0 to 20 := 0;
begin
    process
    begin
        if rising_edge(click) then
            temp2<=0;
            clear<='0';
            t_unlock<='0';
        else
            temp2<=temp2+1 after 15 ns;
        end if;
        if temp2=6 then
            clear<='1';
        elsif temp2=20 then
            t_unlock<='1';
        end if;
    end process;
end Behavioral;

我写了这段代码。编译器说：

Signal temp2 cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.

我在stackoverflow上搜索过。他们说The error 'bad synchronous description' usually means that you have described a register (clocked element) that does not exist in the hardware.但我不知道如何解决我的问题。

Answer 1

VHDL 必须遵循一些综合工具特定的编码指南，以便该工具能够将 VHDL 代码转换为 FPGA 实现。对于异步复位触发器的实现，样式可以是：

process (clk, rst) is
begin
  -- Clock
  if rising_edge(clk) then
    ... -- Update at clock
  end if;
  -- Asynchronous reset
  if rst = '1' then
    ... -- Update at reset
  end if;
end process;

就您的代码而言，您似乎没有使用异步重置，因此模板可能会简化为：

process (clk) is
begin
  if rising_edge(clk) then
    ... -- Update at clock
  end if;
end process;

现在的练习是让您将代码适合该模板，不幸的是，根据提供的代码很难确定确切的意图。

Answer 2

您的代码似乎混合了 HDL 和“软件”语言的概念。我不确定它应该做什么，但我会将它重构为下面的代码

architecture Behavioral of timer is
    constant COUNTER_VALUE_TO_REACH_15ns : integer := <some value>;

    signal temp2   : integer range 0 to 20 := 0;
    signal divider : std_logic_vector(7 downto 0) := (others => '0');
begin
    process
    begin
        -- Everything happens when the clock ticks, except for reset
        if rising_edge(click) then
            temp2    <= 0;
            clear    <= '0';
            t_unlock <= '0';

            -- Count how many cycles until we need to increment temp2
            if divider = COUNTER_VALUE_TO_REACH_15ns then
                temp2   <= temp2 + 1;
                divider <= (others => '0'); -- Reset the counter when we reach the required amount of time
            else
                divider <= divider + 1;
            end if;

            if temp2 = 6 then
                clear <= '1';
            elsif temp2 = 20 then
                t_unlock <= '1';
            end if;

        else
        end if;
    end process;
end Behavioral;