FSM：看不到波形输出答案

【问题标题】：FSM: Can't see output in waveformFSM：看不到波形输出
【发布时间】：2019-05-21 22:42:32
【问题描述】：

我创建了一个有限状态机/数据路径，我正在 ModelSim 中进行调试。状态为加载、增量和完成。状态似乎进展顺利，但是 countx 和 County（内部信号）在增量状态中没有增加，因此 vga_x、vga_y 输出没有被分配。

我尝试将 countx 和 County 信号从逻辑更改为 reg，但这没有任何区别。还尝试将输出信号设置为阻塞，因为我希望 countx 和 County 在它们以相同状态递增后分配给输出。

module fillscreen(input logic clk, input logic rst_n, input logic [2:0] colour,
              input logic start, output logic done,
              output logic [7:0] vga_x, output logic [6:0] vga_y,
              output logic [2:0] vga_colour, output logic vga_plot);

 enum logic [1:0] {Load = 2'b00, Increment = 2'b01, Out = 2'b10, Finish = 2'b11} state, next_state;
 reg[7:0] countx;
 reg [6:0] county;

 always @ (posedge clk) begin
    state = Load;
    case(state)

    Load: begin
           if(rst_n == 0) 
            next_state <= Load; 
        else if (start == 1) 
            next_state <= Increment;
        else begin
        next_state <= Load; end
    //initialize counter
    countx <= 0;    
    county <= 0; end

    Increment: begin
        if(rst_n == 0) 
            next_state <= Load;
        else if (county < 119 && countx < 159) begin
            county <= county+1; 
            next_state <= Increment; end                
        else if (countx < 159) begin
            countx <= countx +1;
            next_state <= Increment; end
        else begin 
            next_state <= Finish;end
    //output            
    vga_y = county;
    vga_x = countx;
    vga_colour = countx % 8;            
    vga_plot = 1;
    end
    Finish: begin
        done <= 1;          
        if(rst_n == 0) 
            next_state <= Load; 
        else begin
            next_state <= Finish; end
    end
    default: begin 
        vga_y = county;
        vga_x = countx;
        done = 0;
        vga_plot = 0;
    end
    endcase
    state = next_state;
end  
endmodule

【问题讨论】：

标签： system-verilog register-transfer-level

【解决方案1】：

请注意，总是阻塞是从头到尾按程序进行评估的。你的第一行是

always @(posedge clk) begin
state = Load;
...

这会在块执行时将状态设置为“加载”并从中删除先前设置的状态

state = next_state;

这意味着每个时钟周期，case(state) 块都会沿着 Load 路径前进。

我建议将 FSM 状态设置在它自己的 always 块中以简化代码。

always @(posedge clk) begin
    if(!rst_n) begin
        state <= Load;
    end
    else begin
        state <= next_state;
    end
end

这样，您可以专注于使用“state”作为输入，使用“next_state”作为原始 always 块的输出。

【讨论】：