【发布时间】：2021-04-02 21:35:35
【问题描述】：
在我的作业中，有人问我一个问题，即使用 verilog HDL 中的状态图设计一台 ATM 机。我以这种方式设计但它没有显示正确的输出实际上没有显示任何输出。任何人都可以检查吗？图片中附有用于此的状态图。
使用具有以下特点的 Mealy 模型设计虚拟/数字 ATM 机：
(i) 有现金且机器准备就绪时闪烁绿灯
(ii) 没有现金或机器出现故障时闪烁红灯
(iii) 插入卡片时，如果卡片合法或未损坏，它会要求输入密码，否则返回 要求重新提交的消息。
(iv) 如果输入了错误的密码，则在第一时间要求重新输入密码，当第二时间 进入也是错误的，取卡进去，发出警报，然后回到休息状态。
(v) 如果别针是对的，则提示要分配的金额。
(vi) 如果金额多于商店，则表示现金不足并进入休息状态。
(vii) 如果数量少于商店，则分配数量并返回休息状态。
module Mealy_atm (output reg
green,red,askpin,carddam,insuf,alarm,askamt,wrongpin,collect,input cash,legal, clock, reset,input
[2:0]epin,amt,prepin,arepin,bal); //module for atm
reg [2: 0] state, next_state; //reg variables for states
wire pin,wpin,equ,les; //wire variables required
parameter S0 = 3'b000, S1 = 3'b001, S2 = 3'b010, S3 = 3'b011,S4 =3'b100; //required parameters
comparator M1 (pin,wpin,epin,prepin); //instantiation of comparator
comparator M2 (equ,les,amt,bal); //instantiation of comparator for amount
assign amtok=equ||les; //assigning value of amtok
comparator M3 (repin,wpin,arepin,prepin); //instantiation of comparator for repin
always @ ( posedge clock, negedge reset) //always block for block
begin //begin of always block
if (reset == 0) state <= S0; //reset of states
else state <= next_state; //assigning next state
end //end of always block
always @ (state,cash,legal,pin,amtok,repin) //always for nextstate caluculation
begin //begin for always block
case (state) //case for assigning next state depending on next state
S0: if (cash) next_state <= S1; else next_state <= S0; //next state if cash is present in atm
S1: if (legal) next_state <= S2; else next_state <= S1; //next state if card is legal
S2: if (pin) next_state <= S3; else next_state <= S4; //next state if pin is correct
S3: if (amtok) next_state <= S1; else next_state <= S1; //next state if amount is less than balance
//in atm
S4: if (repin) next_state<= S3; else next_state <= S1; //next state re-entered pin is correct
endcase //end of case
end //end of always block
always @ (state) //always block for outputs
begin //begin for always block
case (state) //case for different outputs in different in states
S0: begin //begin for outputs for S0 state
carddam <=1'b0; //outputs for S0 state
insuf<=1'b0; //outputs for S0 state
collect <=1'b0; //outputs for S0 state
alarm<=1'b0; //outputs for S0 state
askamt<=1'b0; //outputs for S0 state
askpin<=1'b0; //outputs for S0 state
wrongpin<=1'b0; //outputs for S0 state
green<=1'b0; //outputs for S0 state
if(!cash) red <=1'b1; //outputs for S0 state
end //end for outputs for S0 state
S1: begin //begin for outputs for S1 state
red <=1'b0; //outputs for S1 state
insuf<=1'b0; //outputs for S1 state
collect <=1'b0; //outputs for S1 state
alarm<=1'b0; //outputs for S1 state
askamt<=1'b0; //outputs for S1 state
askpin<=1'b0; //outputs for S1 state
wrongpin<=1'b0; //outputs for S1 state
green<=1'b1; //outputs for S1 state
if(!legal) carddam<=1'b1; //outputs for S1 state
end //end for outputs for S1 state
S2: begin //begin for outputs for S2 state
red <=1'b0; //outputs for S2 state
insuf<=1'b0; //outputs for S2 state
collect <=1'b0; //outputs for S2 state
alarm<=1'b0; //outputs for S2 state
askamt<=1'b0; //outputs for S2 state
green<=1'b1; //outputs for S2 state
carddam <=1'b0; //outputs for S2 state
askpin<=1'b1; //outputs for S2 state
if(!pin) wrongpin<=1'b1; //outputs for S2 state
end //end for outputs for S2 state
S3: begin //begin for outputs for S3 state
red <=1'b0; //outputs for S3 state
alarm<=1'b0; //outputs for S3 state
askamt<=1'b0; //outputs for S3 state
wrongpin<=1'b0; //outputs for S3 state
green<=1'b1; //outputs for S3 state
carddam <=1'b0; //outputs for S3 state
askpin<=1'b1; //outputs for S3 state
if(~amtok) insuf<=1'b1; //outputs for S3 state
else collect <=1'b1 ; //outputs for S3 state
end //end for outputs for S3 state
S4: begin //begin for outputs for S4 state
red <=1'b0; //outputs for S4 state
insuf<=1'b0; //outputs for S4 state
collect <=1'b0; //outputs for S4 state
askpin<=1'b0; //outputs for S4 state
wrongpin<=1'b0; //outputs for S4 state
green<=1'b1; //outputs for S4 state
carddam <=1'b0; //outputs for S4 state
if(repin) askamt<=1'b1; //outputs for S4 state
else alarm<=1'b1; //outputs for S4 state
end //end for outputs for S4 state
endcase //end of case
end //end of case
endmodule //end of module
module comparator(output reg less,equal,input [2:0] Data_in_A,Data_in_B); //module for
//comparaing two inputs
always @ (Data_in_A , Data_in_B) //always for inputs
if(Data_in_A == Data_in_B) //if block for equality
begin //begin for if block
less <= 1'b0; //less value assigning
equal<= 1'b1; //equal value assigning
end //end of begin
else if(Data_in_A < Data_in_B) //if block for less
begin //begin for if block
less <= 1'b1; //less value assigning
equal<= 1'b0; //equal value assingning
end //end of begin of if
else //else for other things
begin //begin for else
less<=1'b0; //less value assigning
equal<=1'b0; //equal value assigning
end //end of else block
endmodule //end of module
// Test bench is
module t_atm; //module for test bench
wire t_green,t_red,t_askpin,t_carddam,t_insuf,t_alarm,
t_askamt,t_wrongpin,t_collect;
//output variables
reg t_cash,t_legal, t_clock,t_reset; //input variables
reg [2:0] t_epin,t_amt,t_prepin,t_arepin,t_bal; //input variables
Mealy_atm M1
(t_green,t_red,t_askpin,t_carddam,t_insuf,t_alarm,
t_askamt,t_wrongpin,t_collect ,t_cash,t_legal,
t_clock,t_reset,t_epin,t_amt,t_prepin,t_arepin,t_bal);
//instantiation of Mealy_atm
initial #100 $finish; //termination time
initial //initial for clock signal
begin //begin of clock signal initial
t_clock=1'b0; //initial clock signal
forever #5 t_clock=~t_clock; //forever loop
end //end of initial block
initial //initial for assigning inputs
begin //begin for initial block
t_reset=1'b1; //input value of reset
#6 t_reset =1'b0;t_prepin=3'b000;t_bal=3'b111; //input values
#4 t_cash=1'b1; //input values
#5 t_legal=1'b1; //input values
#5 t_epin=3'b001; //input values
#5 t_amt=3'b001; //input values
end //end of initial block //input values
endmodule //end of module //input values
【问题讨论】：
标签： verilog