【发布时间】：2019-09-25 07:14:07
【问题描述】：
大家好，我想通过 FSM 生成两个波形或信号（比如说模式 1 和模式 2 信号），每个都有三个脉冲，比如说 P1、P2 和 P3。这些脉冲的宽度为每个 0.8us。 对于模式 1，P1 和 p2 相距 2 us，p1 和 p3 相距 8 us（从脉冲开始） 对于 Mode-2，P1 和 P2 同上，而 P3 相距 21 us。
在 1 毫秒后，这些脉冲会自我重复。 我一直使用 50 Mhz 作为我的输入时钟频率。
我使用 FSM 编写的以下代码
-----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Signal_pulse is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
modes : in STD_LOGIC_VECTOR (2 downto 0);
P_out : out STD_LOGIC);
end signal_pulse;
architecture Behavioral of signal_pulse is
type state_type is (P0, P1, P2, P3);
signal Next_state, Present_state : state_type;
signal count : integer range 0 to 100000000;
signal temp : integer range 0 to 100000000;
begin
Process(rst, clk)
begin
if(rst = '1') then
Present_state <= P0;
elsif(rising_edge(clk)) then
temp <= temp +1;
Present_state <= Next_state;
if (temp = 50000) then
temp <= 1;
end if;
--count <= count+1;
end if;
end process;
state_Process: Process(Present_state)
begin
case present_state is
when P0 =>
if (rst ='1') then
P_out <= '0';
count <= 0;
next_state <= P0;
else
count <= 0;
next_state <= P1;
end if;
when P1 =>
if(modes = "001") then
if (count<40) then
P_out <= '1';
count <= count+1;
next_state <= p1;
elsif(count < 100) then
P_out <= '0';
count <= count+1;
next_state <= p1;
elsif(count = 100) then
next_state <= p2;
end if;
elsif (modes = "010") then
if (count<40) then
P_out <= '1';
count <= count+1;
next_state <= p1;
elsif(count < 100) then
P_out <= '0';
count <= count+1;
next_state <= p1;
elsif(count = 100) then
next_state <= p2;
end if;
else
P_out <= '0';
end if;
when P2 =>
if(modes = "001") then
if (count < 140) then
P_out <= '1';
count <= count+1;
next_state <= p2;
elsif(count < 400) then
P_out <= '0';
count <= count+1;
next_state <= p2;
elsif(count = 400) then
next_state <= P3;
end if;
elsif (modes = "010") then
if (count < 140) then
P_out <= '1';
count <= count+1;
next_state <= p2;
elsif(count < 1050) then
P_out <= '0';
count <= count+1;
next_state <= p2;
elsif(count = 1050) then
next_state <= P3;
end if;
else
P_out <= '0';
end if;
when P3 =>
if(modes = "001") then
if (count < 440) then
count <= count +1;
P_out <= '1';
next_state <= p3;
elsif (temp = 50000) then
count <= 0;
--temp <= 1;
next_state <= P1;
else
P_out <= '0';
next_state <= P3;
end if;
elsif(Modes = "010") then
if (count < 1090) then
count <= count +1;
P_out <= '1';
next_state <= P3;
elsif (temp = 50000) then
count <= 0;
--temp <= 1;
next_state <= P1;
else
P_out <= '0';
next_state <= P3;
end if;
else
P_out <= '0';
end if;
end case;
end Process;
end Behavioral;
但我的输出一直处于高位。请建议我做错了什么。 任何帮助将不胜感激 如果有愚蠢的错误，请原谅我，我是初学者，刚刚进入 vhdl 2 周 谢谢
我还对代码进行了一些更改，如模式 1 的图像所示，我在开始时和重复 1 毫秒后都得到了正确的信号。 但是对于模式 2，当模式 2 启动时，我没有得到正确的脉冲，但在 1 毫秒重复后，我得到了模式 2 信号的正确脉冲。
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标签： vhdl xilinx-ise