实时仿真 Quartus II 出错答案

【问题标题】：Error on real time simulation Quartus II实时仿真 Quartus II 出错
【发布时间】：2014-03-20 18:07:31
【问题描述】：

我正在学习如何在 Quartus II 上使用时间仿真来查看电路中的实际延迟，但出现了错误。这个错误表明我不尊重触发器的保持时间。在逻辑模拟中，电路工作。下来可以看到代码：

module AddTestParalellIf(clk,reset, sum, out);

  input clk, reset;
  output sum, out; 
  reg [15:0] sum;
  reg out ;

  always @(posedge clk ) begin
    if (reset) begin
      sum = 0;
      out = 0;
    end
    else 
    if (sum == 16'b0000000010000010)
      out = 1;
    sum = sum + 1;
  end

endmodule

和错误：

Time: 0 ps  Iteration: 0  Instance: /AddTestParalellIf_vlg_vec_tst File:    plataformadetestes.vt
# ** Error: c:/altera/13.0/modelsim_ase/win32aloem/../altera/verilog /src/cycloneii_atoms.v(5351): $hold( posedge clk &&& nosloadsclr:27871 ps, datain:27922 ps, 286 ps );
#    Time: 27922 ps  Iteration: 0  Instance: /AddTestParalellIf_vlg_vec_tst/i1/\sum[1]~reg0 
# ERROR! Vector Mismatch for output port out :: @time = 1000000.000 ps
#      Expected value = 0
#      Real value = x
# ERROR! Vector Mismatch for output port sum[1] :: @time = 1000000.000 ps
#      Expected value = 0000000000000000
#      Real value = xxxxxxxxxxxxxxx0
# ERROR! Vector Mismatch for output port sum[2] :: @time = 1000000.000 ps
#      Expected value = 0000000000000000
#      Real value = xxxxxxxxxxxxxxx0
# ERROR! Vector Mismatch for output port sum[3] :: @time = 1000000.000 ps
#      Expected value = 0000000000000000
#      Real value = xxxxxxxxxxxxxxx0
# ERROR! Vector Mismatch for output port sum[4] :: @time = 1000000.000 ps
#      Expected value = 0000000000000000
#      Real value = xxxxxxxxxxxxxxx0
# ERROR! Vector Mismatch for output port sum[5] :: @time = 1000000.000 ps
#      Expected value = 0000000000000000
#      Real value = xxxxxxxxxxxxxxx0
# ERROR! Vector Mismatch for output port sum[6] :: @time = 1000000.000 ps
#      Expected value = 0000000000000000
#      Real value = xxxxxxxxxxxxxxx0
# ERROR! Vector Mismatch for output port sum[7] :: @time = 1000000.000 ps
#      Expected value = 0000000000000000
#      Real value = xxxxxxxxxxxxxxx0
# ERROR! Vector Mismatch for output port sum[8] :: @time = 1000000.000 ps
#      Expected value = 0000000000000000
#      Real value = xxxxxxxxxxxxxxx0
# ERROR! Vector Mismatch for output port sum[9] :: @time = 1000000.000 ps
#      Expected value = 0000000000000000
#      Real value = xxxxxxxxxxxxxxx0
# ERROR! Vector Mismatch for output port sum[10] :: @time = 1000000.000 ps
#      Expected value = 0000000000000000
#      Real value = xxxxxxxxxxxxxxx0
# ERROR! Vector Mismatch for output port sum[11] :: @time = 1000000.000 ps
#      Expected value = 0000000000000000
#      Real value = xxxxxxxxxxxxxxx0
# ERROR! Vector Mismatch for output port sum[12] :: @time = 1000000.000 ps
#      Expected value = 0000000000000000
#      Real value = xxxxxxxxxxxxxxx0
# ERROR! Vector Mismatch for output port sum[13] :: @time = 1000000.000 ps
#      Expected value = 0000000000000000
#      Real value = xxxxxxxxxxxxxxx0
# ERROR! Vector Mismatch for output port sum[14] :: @time = 1000000.000 ps
#      Expected value = 0000000000000000
#      Real value = xxxxxxxxxxxxxxx0
# ERROR! Vector Mismatch for output port sum[15] :: @time = 1000000.000 ps
#      Expected value = 0000000000000000
#      Real value = xxxxxxxxxxxxxxx0
# ERROR! Vector Mismatch for output port sum[0] :: @time = 1005000.000 ps
#      Expected value = 0000000000000000
#      Real value = xxxxxxxxxxxxxxx1
#          17 mismatched vectors : Simulation failed !
# ** Note: $finish    : plataformadetestes.vt(463)
#    Time: 10 us  Iteration: 0  Instance: /AddTestParalellIf_vlg_vec_tst/tb_out

我正在使用 quartus II web 上的模型 sim 模拟器

【问题讨论】：

标签： time simulation verilog digital-logic quartus

【解决方案1】：

尝试在else 子句中的两个语句周围添加begin end。如果reset 被断言，您似乎同时清除和递增sum。

【讨论】：