【发布时间】：2015-03-31 21:14:00
【问题描述】：
我正在编写一个基本程序来实现这个链接Network for N=5, using Bose-Nelson Algorithm中的排序算法。
我使用comb.vhd组件比较两个数字，我的程序的顶部实体在下面的代码中。
我用Quartus编译没有问题，但是用modelsim模拟RTL，不管输入是什么，输出总是0000。
我认为我误解了信号的使用，但我不知道哪里出错了。
以下是我程序的主要部分，我使用的信号是：
SIGNAL out0_temp, out1_temp, out3_temp, out4_temp : bit_vector (3 downto 0); --comp1(0,1),comp2(3,4)
SIGNAL out2_temp, out4_1_temp : bit_vector (3 downto 0); --comp3(2,4)
SIGNAL out2_1_temp, out3_1_temp, out1_1_temp, out4_2_temp : bit_vector (3 downto 0); --comp4(2,3),comp5(1,4)
SIGNAL out0_1_temp, out3_2_temp : bit_vector (3 downto 0); --comp6(0,3)
SIGNAL out0_2_temp, out2_2_temp, out1_2_temp, out3_3_temp : bit_vector (3 downto 0); --comp7(0,2),comp8(1,3)
SIGNAL out1_3_temp, out2_3_temp : bit_vector (3 downto 0); --comp9(1,2)
如算法所示，我使用 9 个比较来对输入从最大到最小进行排序，如下所示：
BEGIN
comp1:comp -- (0,1)
PORT MAP (clk,reset, in0, in1, out0_temp, out1_temp);
comp2:comp -- (3,4)
PORT MAP (clk,reset, in3, in4, out3_temp, out4_temp);
comp3:comp -- (2,4)
PORT MAP (clk,reset, in2, out4_temp, out2_temp, out4_1_temp);
comp4:comp -- (2,3)
PORT MAP (clk,reset, out2_temp, out3_temp, out2_1_temp, out3_1_temp);
comp5:comp -- (1,4)
PORT MAP (clk,reset, out1_temp, out4_1_temp, out1_1_temp, out4_2_temp);
comp6:comp -- (0,3)
PORT MAP (clk,reset, out0_temp, out3_1_temp, out0_1_temp, out3_2_temp);
comp7:comp -- (0,2)
PORT MAP ( clk,reset, out0_1_temp, out2_1_temp, out0_2_temp, out2_2_temp);
comp8:comp -- (1,3)
PORT MAP ( clk,reset, out1_1_temp, out3_2_temp, out1_2_temp, out3_3_temp);
comp9:comp -- (1,2)
PORT MAP ( clk,reset, out1_2_temp, out2_2_temp, out1_3_temp, out2_3_temp);
out0 <= out0_2_temp;
out1 <= out1_3_temp;
out2 <= out2_3_temp;
out3 <= out3_3_temp;
out4 <= out4_2_temp;
END ARCHITECTURE behav;
Comp.vhd module
--Comp.vhd 模块用于比较两个数字，如果有则切换它们
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY comp IS
PORT (
clk : IN std_logic;
reset : IN bit;
num0_in : IN bit_vector (3 DOWNTO 0);
num1_in : IN bit_vector (3 DOWNTO 0);
num0_out : OUT bit_vector (3 DOWNTO 0);
num1_out : OUT bit_vector (3 DOWNTO 0)
);
END ENTITY comp;
ARCHITECTURE compare OF comp IS
BEGIN
PROCESS (clk, reset)
BEGIN
-- reset everything to '0' when reset is asserted
IF (reset = '1') THEN
-- num0_out <= (OTHERS => '0');
--num1_out <= (OTHERS => '0');
ELSIF (rising_edge (clk)) THEN
-- num0_in is smaller than num1_in, so switch them
IF (num0_in < num1_in) THEN
num0_out <= num1_in;
num1_out <= num0_in;
-- num0_in and num1_in are in order
ELSE
num0_out <= num0_in;
num1_out <= num1_in;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE compare;
【问题讨论】：
-
我认为答案可以提供的任何见解都需要您的更多代码，特别是对您的实例化comp的可见性。
-
这是我的comp模块，它工作正常，我用modelsim模拟它，它给出了预期的结果：
标签： vhdl sorting-network