Verilog与VHDL的一些比较

1.列表

verilog	VHDL
`include	LIBRARY IEEE
module	ENTITY
	architecture
always	process
wire/reg	signal
assign	<=
=阻塞-组合逻辑
<=非阻塞-时序逻辑
posedge clk(negedge)	clk’event and clk= ‘1’

2.图例

图例来源网络，有空可以敲一遍