VHDL 中的 case 语句错误消息答案

【问题标题】：Case statement error message in VHDLVHDL 中的 case 语句错误消息
【发布时间】：2015-11-30 22:17:31
【问题描述】：

您好，有人可以帮我解决困扰我一段时间的事情。我有一个简单的 case 语句，据我所知，语法很好。看下面的代码

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY D7SEGSEL IS
    PORT (
            SW      :in std_logic_vector(3 DOWNTO 0);
            SEG :out std_logic_vector(6 DOWNTO 0)
            );
END ENTITY D7SEGSEL;

ARCHITECTURE behavioral OF D7SEGSEL IS      
BEGIN
    CASE SW IS
        WHEN "1000000" => SEG <= "0000";
              "1111001" => SEG <= "0001";
              "0100100" => SEG <= "0010";
              "0110000" => SEG <= "0011";
              "0011001" => SEG <= "0100";
              "0010010" => SEG <= "0101";
              "0000010" => SEG <= "0110";
              "1111000" => SEG <= "0111";
              "0000000" => SEG <= "1000";
              "0011000" => SEG <= "1001";
              "0001000" => SEG <= "1010";
              "0000011" => SEG <= "1011";
              "1000110" => SEG <= "1100";
              "0100001" => SEG <= "1101";
              "0000110" => SEG <= "1110";
              "0001110" => SEG <= "1111";
        END CASE;
END ARCHITECTURE behavioral;

它是一个简单的 7SEG LED 驱动器，每次我编译代码时都会收到以下 错误消息：

错误 (10500)：文本附近 D7SEGCASE.vhd(19) 处的 VHDL 语法错误 “案子”;期待“end”，或“(”，或标识符（“case”是保留关键字），或并发语句错误 (10500)：D7SEGCASE.vhd(21) 靠近文本“=>”的 VHDL 语法错误；期待 > "(", 或 “'”或“.”

谁能指出我做错了什么？

我已经使用 select/when 语句为 7seg 制作了解码器，但想练习使用 case，然后通过添加时钟输入使其同步

【问题讨论】：

标签： vhdl

【解决方案1】：

你有一些问题。

您缺少流程说明。
您在第一个条件之后缺少后续的“何时”。
您在 WHEN 条件中颠倒了您的条件和分配。

请参阅以下修复：

ARCHITECTURE behavioral OF D7SEGSEL IS      
BEGIN
    my_case : process(sw, seg)
    begin
        CASE SW IS
            WHEN "0000" => SEG <= "1000000";
            WHEN "0001" => SEG <= "1111001";
            -- Other Assignments follow...
        END CASE;
    end process my_case;
END ARCHITECTURE behavioral;

【讨论】：

感谢您的反馈，非常感谢：)

【解决方案2】：

正如其他人所指出的，您的代码存在一些问题，但幸运的是，有不同的选项可以实现您想要的。

案例（流程）

process (SW) is
begin
  case SW is
    when "0000" => SEG <= "1000000";
    when "0001" => SEG <= "1111001";
    when "0010" => SEG <= "0100100";
    when "0011" => SEG <= "0110000";
    when "0100" => SEG <= "0011001";
    when "0101" => SEG <= "0010010";
    when "0110" => SEG <= "0000010";
    when "0111" => SEG <= "1111000";
    when "1000" => SEG <= "0000000";
    when "1001" => SEG <= "0011000";
    when "1010" => SEG <= "0001000";
    when "1011" => SEG <= "0000011";
    when "1100" => SEG <= "1000110";
    when "1101" => SEG <= "0100001";
    when "1110" => SEG <= "0000110";
    when "1111" => SEG <= "0001110";
    when others => SEG <= (others => 'X');
  end case;
end process;

何时（并发）

SEG <= "1000000" when SW = "0000" else
       "1111001" when SW = "0001" else
       "0100100" when SW = "0010" else
       "0110000" when SW = "0011" else
       "0011001" when SW = "0100" else
       "0010010" when SW = "0101" else
       "0000010" when SW = "0110" else
       "1111000" when SW = "0111" else
       "0000000" when SW = "1000" else
       "0011000" when SW = "1001" else
       "0001000" when SW = "1010" else
       "0000011" when SW = "1011" else
       "1000110" when SW = "1100" else
       "0100001" when SW = "1101" else
       "0000110" when SW = "1110" else
       "0001110" when SW = "1111" else
       (others => 'X');

选择（并发）

d7seg : with SW select
  SEG <= "1000000" when "0000",
         "1111001" when "0001",
         "0100100" when "0010",
         "0110000" when "0011",
         "0011001" when "0100",
         "0010010" when "0101",
         "0000010" when "0110",
         "1111000" when "0111",
         "0000000" when "1000",
         "0011000" when "1001",
         "0001000" when "1010",
         "0000011" when "1011",
         "1000110" when "1100",
         "0100001" when "1101",
         "0000110" when "1110",
         "0001110" when "1111",
         (others => 'X') when others;

Select (concurrent) 紧凑且重复次数少，并且可能会产生小型实现，因此将是一个不错的选择。

【讨论】：

【解决方案3】：

我在你的代码中看不到进程。

process(sw,seg)
.
.
.
end process

添加后检查是否得到

【讨论】：