VHDL中CASE语句中的多个赋值

Question

我还是 VHDL 新手。我需要在 CASE 语句中为多个信号赋值，如下所示：

CASE input24 IS
WHEN "00" THEN 
                    output0 <= '1' ;
                    output1 <= '0' ;
                    output2 <= '0' ;
                    output3 <= '0' ;

WHEN "01" THEN 
                    output0 <= '0' ;
                    output1 <= '1' ;
                    output2 <= '0' ;
                    output3 <= '0' ;

WHEN "10" THEN 
                    output0 <= '0' ;
                    output1 <= '0' ;
                    output2 <= '1' ;
                    output3 <= '0' ;

WHEN "11" THEN 
                    output0 <= '0' ;
                    output1 <= '0' ;
                    output2 <= '0' ;
                    output3 <= '1' ;

在尝试这个之前，我尝试像这样在一行中分配值

WHEN "00" => output0 <= '1', output1 <= '0', output2 <= '0', output3 <= '0' ;

第二个报错了

found '0' definitions of operator "<=", cannot determine exact 
overloaded matching definition for "<="

第一个是语法错误。

我哪里错了？

有没有办法为单个案例的多个信号分配值？

谢谢

Answer 1

使用CASE 时，语法为WHEN "00" =>，因此不使用THEN。这 因此代码是：

CASE input24 IS
  WHEN "00" =>
    output0 <= '1' ;
    output1 <= '0' ;
    output2 <= '0' ;
    output3 <= '0' ;
...

如果input24 是std_logic_vector，则必须在带有WHEN OTHERS => 的情况下处理input24 的剩余编码。代码是：

WHEN OTHERS =>
  output0 <= 'X' ;
  output1 <= 'X' ;
  output2 <= 'X' ;
  output3 <= 'X' ;

要在单个like中编写赋值，仍然使用;作为语句 分隔符，因此不是, 如问题代码所示，然后只需删除 空白。代码是：

WHEN "01" => output0 <= '0'; output1 <= '1'; ...

为了在一个语句中分配多个信号，VHDL-2008 支持 聚合赋值，所以如果你使用 VHDL-2008，你可以这样写：

WHEN "10" =>
  (output3, output2, output1, output0) <= std_logic_vector'("0100");

对于 VHDL-2003，解决方案可能是创建一个中间 output 信号作为 std_logic_vector，然后分配给这个。然后代码可以是：

  ...
  signal output : std_logic_vector(3 downto 0);
begin
  ...
      WHEN "11" =>
        output <= "1000";
  ...
  output0 <= output(0);
  output1 <= output(1);
  output2 <= output(2);
  output3 <= output(3);

如果使用了output，那么case 的确切实现就是 用于设置具有input24 中给出的数字的位可以使用：

LIBRARY IEEE;
USE IEEE.NUMERIC_STD.ALL;

ARCHITECTURE syn OF mdl IS

  SIGNAL output : STD_LOGIC_VECTOR(3 DOWNTO 0);

BEGIN

  PROCESS (input24) IS
  BEGIN
    output <= (OTHERS => '0');
    output(TO_INTEGER(UNSIGNED(input24))) <= '1';
  END PROCESS;

  output0 <= output(0);
  output1 <= output(1);
  output2 <= output(2);
  output3 <= output(3);

END ARCHITECTURE;

否则，如果不使用output信号，那么case仍然可以 通过默认分配为“0”来简化输出，因此使用代码：

ARCHITECTURE syn OF mdl IS
BEGIN

  PROCESS (input24) IS
  BEGIN
    output0 <= '1' ;
    output1 <= '0' ;
    output2 <= '0' ;
    output3 <= '0' ;
    CASE input24 IS
      WHEN "00" => output0 <= '1' ;
      WHEN "01" => output1 <= '1';
      WHEN "10" => output2 <= '1' ;
      WHEN "11" => output3 <= '1' ;
      WHEN OTHERS => output0 <= 'X'; output1 <= 'X'; output2 <= 'X'; output3 <= 'X';
    END CASE;
  END PROCESS;

END ARCHITECTURE;

Answer 2

我认为问题是“那么”

CASE input24 IS
WHEN "00" => 
                    output0 <= '1' ;
                    output1 <= '0' ;
                    output2 <= '0' ;
                    output3 <= '0' ;

WHEN "01" =>
                    output0 <= '0' ;
                    output1 <= '1' ;
                    output2 <= '0' ;
                    output3 <= '0' ;

WHEN "10" =>
                    output0 <= '0' ;
                    output1 <= '0' ;
                    output2 <= '1' ;
                    output3 <= '0' ;

WHEN "11" =>
                    output0 <= '0' ;
                    output1 <= '0' ;
                    output2 <= '0' ;
                    output3 <= '1' ;
END CASE;