VHDL - 时钟边沿之外的值编码错误

Question

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity RAM_controler is 
port(
      clk_50 : in std_logic;
      clk_baud : in std_logic;
      main_reset : in std_logic;
      enable: in std_logic; --active high write enable
      in_data : in std_logic_vector(7 downto 0);
      W_order : out std_logic; 
      R_order : out std_logic;
      Data_OUT : out std_logic_vector(7 downto 0);
      Write_Address_OUT: out std_logic_vector(7 downto 0);  
      Read_Address_OUT: out std_logic_vector(7 downto 0)          
      );
end entity RAM_controler;
architecture Behavioral of RAM_controler is
type state is (reset,operation);
signal state_reg,next_state_reg : state;
signal write_address : std_logic_vector(W-1 downto 0):="00000000"; 
signal next_write_address : std_logic_vector(W-1 downto 0):="00000000";         
begin   
state_change : process(clk_50, main_reset)
begin
    if (main_reset = '1') then
        state_reg <= reset;     
    elsif (rising_edge(clk_50)) then
        state_reg <= operation;
        read_counter <= next_read_counter;
        write_address<= next_write_address;
        read_address <= next_read_address;
    end if;     
end process;

writecounter : process(clk_baud, main_reset,enable) 
begin
    if (main_reset='1') then
        next_write_address <= "00000000";
        Data_OUT <= "ZZZZZZZZ";
        W_order <='0';
        Write_Address_OUT <="ZZZZZZZZ";
    elsif (rising_edge(clk_baud) and enable='1' ) then
        W_order <='1';
        Data_OUT <= in_data;            
        Write_Address_OUT <= write_address;
        if (write_address = "11111111") then
            next_write_address <= "00000000";
        else
            next_write_address <= write_address+1;
        end if;
    else 
        W_order <='0';
        Write_Address_OUT <= "ZZZZZZZZ";
        next_write_address <= write_address+1;
    end if;
end process;        
end Behavioral;

以上代码描述的是 RAM 控制器。

产生问题的部分是“elsif (rising_edge(clk_baud) and enable='1') then”。

错误：无法在 RAM_controler.vhd 中为“Write_Address_OUT”注册，因为它在时钟边沿之外没有保持其值

我不知道为什么那一点是错误的。

有人给我建议吗？

谢谢！

Answer 1

如果您要编写顺序逻辑代码，最好坚持使用模板。这是一个这样的模板，用于具有异步复位的时序逻辑，所有综合工具都应该理解：

process(clock, async_reset)  -- nothing else should go in the sensitivity list
begin
    -- never put anything here
    if async_reset ='1' then  -- or '0' for an active low reset
        -- set/reset the flip-flops here
        -- ie drive the signals to their initial values
    elsif rising_edge(clock) then  -- or falling_edge(clock)
        -- put the synchronous stuff here
        -- ie the stuff that happens on the rising or falling edge of the clock
    end if;
     -- never put anything here
end process;        

所以 enable 不应该在敏感列表中，也不应该在与异步重置和时钟测试相同的 if 语句中进行测试。

您收到此错误的原因：

错误：无法在“Write_Address_OUT”处注册 RAM_controler.vhd，因为它不在时钟之外保持其值 边缘

是因为代码中的最后三个赋值：

            W_order <='0';
            Write_Address_OUT <= "ZZZZZZZZ";
            next_write_address <= write_address+1;

可以发生在时钟的下降沿或（因为您的灵敏度列表中也有 enable）完全独立于任何时钟。逻辑合成器无法合成具有这种行为的逻辑。如果你坚持使用模板，你就不会遇到这种问题（它会让你更加仔细地思考你期望合成器合成什么逻辑）。

所以，我会将您的 writecounter 过程编码得更像这样：

writecounter : process(clk_baud, main_reset) 
begin
    if (main_reset='1') then
        next_write_address <= "00000000";
        Data_OUT <= "ZZZZZZZZ";
        W_order <='0';
        Write_Address_OUT <="ZZZZZZZZ";
    elsif rising_edge(clk_baud) then
        if enable='1' then
            W_order <='1';
            Data_OUT <= in_data;            
            Write_Address_OUT <= write_address;
            if (write_address = "11111111") then
                next_write_address <= "00000000";
            else
                next_write_address <= write_address+1;
            end if;
        else 
            W_order <='0';
            Write_Address_OUT <= "ZZZZZZZZ";
            next_write_address <= write_address+1;
        end if;
    end if;
end process;        

不过，我应该强调我的代码与您的代码不完全一样。我不知道你的设计意图，所以我只能猜测你的意图。如果您打算进行其他一些行为，那么您将不得不实现它。不管你的设计意图是什么，我关于坚持使用模板的建议仍然很重要。

Answer 2

代码中最后的else 实际上应该是：

elsif (rising_edge(clk_baud) and enable='0' ) then