分配给 UInt 的各个位的凿子答案

【问题标题】：Chisel assigning to individual bits of UInt分配给 UInt 的各个位的凿子
【发布时间】：2017-01-11 02:15:24
【问题描述】：

有人可以告诉我为什么以下代码不会在 Chisel 中详细说明吗？看来我无法分配给 UInt 中的各个位。这是设计使然吗？

我确实看到了 Jack 对类似问题的回答，但以下跨链位的逻辑类型很常见，并且在 SV 等中很容易参数化。我可以看到创建布尔向量以及各个位，但是仍然是如何回到 UInt 的问题......

  def ffo(pwidth:Int, in:UInt) : UInt = {
    val rval = Wire(UInt(width=pwidth))
    rval(0) := in(0)
    for(w <- 1 until pwidth) {
      rval(w) := in(w) & !( in(w-1,0).orR() )
    }
    rval
  }

结果：

firrtl.passes.CheckGenders$WrongGender:  @[Misc.scala 21:13:@5808.4]: [module IuIrRename]  Expression T_1824 is used as a FEMALE but can only be used as a MALE.
firrtl.passes.CheckGenders$WrongGender:  @[Misc.scala 23:15:@5815.4]: [module IuIrRename]  Expression T_1826 is used as a FEMALE but can only be used as a MALE.
firrtl.passes.CheckGenders$WrongGender:  @[Misc.scala 23:15:@5822.4]: [module IuIrRename]  Expression T_1834 is used as a FEMALE but can only be used as a MALE.
firrtl.passes.CheckGenders$WrongGender:  @[Misc.scala 23:15:@5829.4]: [module IuIrRename]  Expression T_1842 is used as a FEMALE but can only be used as a MALE.
firrtl.passes.CheckGenders$WrongGender:  @[Misc.scala 21:13:@5834.4]: [module IuIrRename]  Expression T_1851 is used as a FEMALE but can only be used as a MALE.

【问题讨论】：

标签： chisel

【解决方案1】：

在继续实验（并查看生成的 Verilog 之后）后，以下代码与我正在寻找的代码等效：

  def ffo(pwidth:Int, in:UInt) : UInt = {
    val ary = Wire(Vec(pwidth, Bool()))
    ary(0) := in(0)
    for(w <- 1 until pwidth) {
      ary(w) :=   in(w) && !( in(w-1,0).orR() )
    }
    val rval = Reverse(Cat(ary))
    rval
  }

【讨论】：