【发布时间】:2021-03-19 22:34:19
【问题描述】:
我正在尝试为要传递给模块的数组中的接口提供唯一 ID:
1 // Test case for SO question on SystemVerilog array parameterization.
2 //
3 // Original author: David Banas <david@luminouscomputing.com>
4 // Original date: March 19, 2021
5
6 interface intf
7 #( parameter ID = 0
8 ) ();
9
10 logic data;
11 endinterface
12
13 module foo
14 #( parameter N_IFS = 1
15 )( intf ifs[N_IFS]
16 );
17
18 initial begin
19 $display($sformatf("ID of last interface: %0d.", ifs[N_IFS-1].ID));
20 end
21 endmodule : foo
22
23 module top;
24 localparam N_IFS = 2;
25
26 intf ifs[N_IFS]();
27
28 genvar i;
29 generate
30 for(i=0; i<N_IFS; i++)
31 defparam ifs[i].ID = i;
32 endgenerate
33
34 foo #(.N_IFS(N_IFS)) u_foo(.ifs(ifs));
35 endmodule : top
我的 SystemVerilog 编译器出现了这个错误:
Error-[SVDOGH] Invalid defparam on a parameter
/home/david/tmp/array_params.sv, 31
Defparam on a parameter outside the generated hierarchy.
Reference to 'ID' in defparam in instance 'top.ifs[0]' at
/home/david/tmp/array_params.sv, 31 is invalid.
Target parameter 'ID' must resolve in the generated hierarchy
'top.genblk1[0]' starting at /home/david/tmp/array_params.sv, 30.
我怎样才能做到这一点?
【问题讨论】: