尝试在 Verilog 中创建循环仲裁器答案

【问题标题】：Trying to create a Round Robin Arbiter in Verilog尝试在 Verilog 中创建循环仲裁器
【发布时间】：2014-04-04 00:38:43
【问题描述】：

所以我试图让我的 RR 仲裁器使用测试平台输出正确的值，但是当状态正确转换时，输出总是设置为默认值，16'h0000。任何想法为什么这个值不会改变？

这是我的设计：

module RRArbiter(input [15:0]NodeRequests,
                      //input clock,
                      output reg [15:0]ArbiterOut
                      );    

reg[4:0]state;
reg[4:0] next_state;
parameter [4:0]IDLE = 5'b00000,
s_0 = 5'b00001,
s_1 = 5'b00010,
s_2 = 5'b00011,
s_3 = 5'b00100,
s_4 = 5'b00101,
s_5 = 5'b00110,
s_6 = 5'b00111,
s_7 = 5'b01000,
s_8 = 5'b01001,
s_9 = 5'b01010,
s_10 = 5'b01011,
s_11 = 5'b01100,
s_12 = 5'b01101,
s_13 = 5'b01110,
s_14 = 5'b01111,
s_15 = 5'b10000;

//Clock Gen
reg clock;
parameter duty_cycle = 2;
initial 
begin: clock_loop
clock = 0;
forever
<pound>duty_cycle clock = ~clock;
end
initial
<pound>10000 disable clock_loop;

initial begin
state = IDLE;
ArbiterOut = 16'h0000;
end

always @ (posedge clock)
begin
state = next_state;
case(state)

IDLE : begin

casex(NodeRequests)
16'bxxxxxxxxxxxxxxx1 : next_state = s_0;
16'bxxxxxxxxxxxxxx1x : next_state = s_1;
16'bxxxxxxxxxxxxx1xx : next_state = s_2;
16'bxxxxxxxxxxxx1xxx : next_state = s_3;
16'bxxxxxxxxxxx1xxxx : next_state = s_4;
16'bxxxxxxxxxx1xxxxx : next_state = s_5;
16'bxxxxxxxxx1xxxxxx : next_state = s_6;
16'bxxxxxxxx1xxxxxxx : next_state = s_7;
16'bxxxxxxx1xxxxxxxx : next_state = s_8;
16'bxxxxxx1xxxxxxxxx : next_state = s_9;
16'bxxxxx1xxxxxxxxxx : next_state = s_10;
16'bxxxx1xxxxxxxxxxx : next_state = s_11;
16'bxxx1xxxxxxxxxxxx : next_state = s_12;
16'bxx1xxxxxxxxxxxxx : next_state = s_13;
16'bx1xxxxxxxxxxxxxx : next_state = s_14;
16'b1xxxxxxxxxxxxxxx : next_state = s_15;
default : next_state = IDLE;
endcase
end

s_0   : begin
            ArbiterOut = 16'b0000000000000001;
            next_state = s_1;
            end
s_1   :  begin
            ArbiterOut = 16'b0000000000000010;
            next_state = s_2;
            end
s_2   :  begin
            ArbiterOut = 16'b0000000000000100;
            next_state = s_3;
            end
s_3   :  begin
            ArbiterOut = 16'b0000000000001000;
            next_state = s_4;
            end
s_4   :  begin
            ArbiterOut = 16'b0000000000010000;
            next_state = s_5;
            end
s_5   :  begin
            ArbiterOut = 16'b0000000000100000;
            next_state = s_6;
            end
s_6   :  begin
            ArbiterOut = 16'b0000000001000000;
            next_state = s_7;
            end
s_7   :  begin
            ArbiterOut = 16'b0000000010000000;
            next_state = s_8;
            end
s_8   :  begin
            ArbiterOut = 16'b0000000100000000;
            next_state = s_9;
            end
s_9   :  begin
            ArbiterOut = 16'b0000001000000000;
            next_state = s_10;
            end
s_10  :  begin
            ArbiterOut = 16'b0000010000000000;
            next_state = s_11;
            end
s_11  :  begin
            ArbiterOut = 16'b0000100000000000;
            next_state = s_12;
            end
s_12  :  begin
            ArbiterOut = 16'b0001000000000000;
            next_state = s_13;
            end
s_13  :  begin
            ArbiterOut = 16'b0010000000000000;
            next_state = s_14;
            end
s_14  :  begin
            ArbiterOut = 16'b0100000000000000;
            next_state = s_15;
            end
s_15  :  begin
            ArbiterOut = 16'b1000000000000000;
            next_state = s_0;
            end

default  : begin
                ArbiterOut = 16'hxxxx;
                state = IDLE;
                end

endcase

end


endmodule

【问题讨论】：

标签： verilog xilinx modelsim synthesis register-transfer-level

【解决方案1】：

所以您的问题是您分配了state = next_state，但从未定义过next_state！由于 next_state 未定义，因此您的 state 将变为默认值。默认情况下，您将state 分配回IDLE（因此为什么在时钟之间您看到state 空闲，但您仍然从未分配next_state。第二个时钟来了，您一遍又一遍地做同样的事情，因为next_state 是从未定义。解决此问题的一种方法是在您分配 state 的同一初始块中将 next_state 分配给某个值。

我在初始块和默认情况下都分配了next_state，它工作正常。

【讨论】：