/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
* @{
*/
#define TIM_TRGO_RESET 0x00000000U
#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
/** @defgroup TIM_Clock_Source TIM Clock Source
* @{
*/
#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
* @{
*/
#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)