FPGA + Quartus II + Verilog+ ASKMOD ( The Second Chapter)

 The Second Chapter：

Create an IP core (NCO core) in the ASKMod project

 

FPGA + Quartus II + Verilog+ ASKMOD ( The Second Chapter)

FPGA + Quartus II + Verilog+ ASKMOD ( The Second Chapter) 

FPGA + Quartus II + Verilog+ ASKMOD ( The Second Chapter) 

 FPGA + Quartus II + Verilog+ ASKMOD ( The Second Chapter)

 保存到默认的工程目录下，IP核名字取为dds（注意里面的source文件是自己建的，用于放源代码）

 FPGA + Quartus II + Verilog+ ASKMOD ( The Second Chapter)

 FPGA + Quartus II + Verilog+ ASKMOD ( The Second Chapter)

FPGA + Quartus II + Verilog+ ASKMOD ( The Second Chapter)

 FPGA + Quartus II + Verilog+ ASKMOD ( The Second Chapter)

 FPGA + Quartus II + Verilog+ ASKMOD ( The Second Chapter)

FPGA + Quartus II + Verilog+ ASKMOD ( The Second Chapter) 

FPGA + Quartus II + Verilog+ ASKMOD ( The Second Chapter) 

FPGA + Quartus II + Verilog+ ASKMOD ( The Second Chapter) 

FPGA + Quartus II + Verilog+ ASKMOD ( The Second Chapter) 

FPGA + Quartus II + Verilog+ ASKMOD ( The Second Chapter) 

FPGA + Quartus II + Verilog+ ASKMOD ( The Second Chapter)

 July 26th 2018

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