always @ (posedge clk_1)
begin
if(rst_n)
rs_din <= 0;
else if(!CH_Channel_ONOFF)
rs_din <= 0;
else
case(addr)
0:rs_din <= 8'h41;
1:rs_din <= 8'h83;
2:rs_din <= cnt_frame_dummy[23:16];
3:rs_din <= cnt_frame_dummy[15:8];
4:rs_din <= cnt_frame_dummy[7:0];
5:rs_din <= 0;
6,7,8,9,10,11,12,13:
rs_din <= 0;
14:rs_din <= 8'h3F;
15:rs_din <= 8'hFF;
16:rs_din <= 8'hFA;
17:rs_din <= 8'hCC;
18:rs_din <= 8'h7A;
19:rs_din <= 8'hBF;
20:rs_din <= cnt_frame[31:24];
21:rs_din <= cnt_frame[23:16];
22:rs_din <= cnt_frame[15:8];
23:rs_din <= cnt_frame[7:0];
default:
if(data_type_sel == 0)
rs_din <= 8'h55;
else if(data_type_sel == 1)
rs_din <= 8'hAA;
else if(data_type_sel == 2)
rs_din <= 8'hFF;
else if(data_type_sel == 3)
rs_din <= fram_data_test;
endcase
end
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