无法编译 VHDL 包 - Modelsim 错误：(vcom-1576) 期待 END

Question

很简单，但我正在拔头发，需要一些新鲜的眼睛。问题在下面详细说明，最初我遇到了一个包含多个项目的更大包裹的问题，因此将所有内容都剥离了基础，仍然无法解决......

提前致谢

g

简单代码：

----------------------------------
--  LIBRARY_DECLARATIONS
----------------------------------
library STD;
use     STD.standard.all;
----------------------------------
library IEEE;
use     IEEE.std_logic_1164.all;
----------------------------------
--  PACKAGE_DECLARATION
----------------------------------
package Dummy_pkg is

   component dummy_comp is
      (
         SIG_IN  : in    std_logic;
         SIG_BI  : inout std_logic;
         SIG_OUT : out   std_logic
      );
   end component dummy_comp;

end package TB_PHAS_FPGA_DUT_pkg;

package body TB_PHAS_FPGA_DUT_pkg is
end package body TB_PHAS_FPGA_DUT_pkg;

这是我从 Modelsim（MS 版）得到的错误：

vcom -reportprogress 300 -work work C:/_WorkDir/pkg_issue/Dummy_pkg.vhd
# Model Technology ModelSim Microsemi vcom 10.5c Compiler 2016.07 Jul 21 2016
# Start time: 13:49:21 on Oct 11,2018
# vcom -reportprogress 300 -work work C:/_WorkDir/pkg_issue/Dummy_pkg.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling package Dummy_pkg
# ** Error: C:/_WorkDir/pkg_issue/Dummy_pkg.vhd(20): near "(": (vcom-1576) expecting END.
# End time: 13:49:21 on Oct 11,2018, Elapsed time: 0:00:00
# Errors: 1, Warnings: 0

Answer 1

你的意思是：

   component dummy_comp is
      port                           --  <--------------------
      (
         SIG_IN  : in    std_logic;
         SIG_BI  : inout std_logic;
         SIG_OUT : out   std_logic
      );
   end component dummy_comp;

Answer 2

知道了 - 我在组件声明中缺少“端口”.... 总是在您发布之后...典型...抱歉浪费时间。
rgds，克。