如何在 VHDL 中使用/声明无符号整数值？

Question

我正在尝试在 Altera DE1-SoC 板上设计一个基本的自动售货机。我的问题来自尝试编写将控制自动售货过程的状态机。您如何跟踪在状态之间跳跃的 $ 价值？我认为我试图实现的代码是用更高级别的语言格式编写的，无法用 VHDL 编译。有什么想法吗？

我收到了这个错误（就在架构声明之后）：

错误 (10482)：State.vhd(21) 处的 VHDL 错误：对象“unsignedInteger” 已使用但未声明

library ieee;
    use ieee.std_logic_1164.all;
    use IEEE.numeric_std.all;
    use IEEE.std_logic_unsigned.all;

    entity MessageState is
    Port(
        Reset          :in   std_logic; -- reset to a safe state
        -----------------------------------------------------------------------------------
        MyStateOut  :out    std_logic_vector( 1 downto 0 ); -- drive the current state to display or LEDs 
        OutputCode  :out    std_logic_vector( 6 downto 0 ) -- to the display driver 
    );

    end;

    architecture Vending_FSM of MessageState is

    signal Count: unsignedInteger(8 downto 0);

    -- we define a data type to represent the states. Use descriptive names
    -- add more lines for more states. Change the size of MyState as needed
    subtype MyState is std_logic_vector(2 downto 0);

    constant Idle          :MyState := "000";
    constant NickelState  :MyState := "001";
    constant DimeState    :MyState := "010";
    constant QuarterState :MyState := "011";
    constant Dispense       :MyState := "100";

    signal state, next_state: MyState;

    begin

    MyStateOut <= state; -- make state visible.

    MyNextState: process(state, next_state) begin -- add all signals read or tested in this process

        case state is

        when Idle =>

            if ( KEY(0) = '1') then
                next_state <= NickelState;

            elsif ( KEY(1) = '1') then
                next_state <= DimeState;

            elsif ( KEY(2) = '1') then
                next_state <= QuarterState;

            else
                next_state <= Idle; -- default action
                Count <= (others => '0');

            end if; 

Answer 1

1) 删除 use IEEE.std_logic_unsigned.all;，因为 numeric_std 已加载。它声明了SIGNED 和UNSIGNED 数据类型。

2) 您的信号 Count 的类型只是 UNSIGNED。