BCD到条形图解码器vhdl设计代码答案

【问题标题】：BCD to bargraph decoder vhdl design codeBCD到条形图解码器vhdl设计代码
【发布时间】：2015-10-01 13:32:10
【问题描述】：

输入表示 0 到 9 之间的二进制值。有九个输出。每个输出驱动一个 LED。当输出为 0 时，其关联的 LED 亮起。当它为 1 时，其关联的 LED 熄灭。 LED 堆叠成竖条。顶部 LED 由 bar_graph(8) 驱动，底部 LED 由 bar_graph(0) 驱动。

我在这里粘贴了我的代码，它有一些错误，我不确定这是否是正确的方法。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

entity bcd_2_bar is 

port (bcd : in std_logic_vector (3 downto 0); 

  bar_graph : out std_logic_vector (8 downto 0)); 

end bcd_2_bar; 

architecture test of bcd_2_bar is

begin

  bar_graph<="111111111" when "0000" else 

  bar_graph<="111111110" when "0001" else

  bar_graph<="111111100" when "0010" else

  bar_graph<="111111000" when "0011" else

  bar_graph<="111110000" when "0100" else 

  bar_graph<="111100000" when "0101" else

  bar_graph<="111000000" when "0110" else

  bar_graph<="110000000" when "0111" else

  bar_graph<="100000000" when "1000" else 

  --nothing is displayed when number greater than nine.

  bar_graph<="111111111" when others;

end test;

【问题讨论】：

您需要检查“条件赋值语句”的正确语法。

标签： vhdl hdl

【解决方案1】：

您没有编写格式正确的语句。您可以执行以下操作之一：

bar_graph <= "111111111" when bcd = "0000" else
             "111111110" when bcd = "0001" else
             "111111100" when bcd = "0010" else
             "111111000" when bcd = "0011" else
             "111110000" when bcd = "0100" else
             "111111111";

或

with bcd select bar_graph <=
             "111111111" when "0000",
             "111111110" when "0001",
             "111111100" when "0010",
             "111111000" when "0011",
             "111110000" when "0100",
             "111111111" when others;

或

process(bcd)
begin
  case bcd is
    when "0000" => bar_graph <= "111111111";
    when "0001" => bar_graph <= "111111110";
    when "0010" => bar_graph <= "111111100";
    when "0011" => bar_graph <= "111111000";
    when "0100" => bar_graph <= "111110000";
    when others => bar_graph <= "111111111";
  end case;
end process;

我没有包括你所有的 bcd 值，但你应该明白。

【讨论】：

【解决方案2】：

或者类似的东西

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std_unsigned.all;

entity bcd_2_bar is
  generic (
    led_on : std_logic := '0');
  port (
    bcd       : in  std_logic_vector(3 downto 0);
    bar_graph : out std_logic_vector(8 downto 0));
end entity bcd_2_bar;

architecture rtl of bcd_2_bar is
begin
  led_driver: process (bcd) is
  begin
    for led in bar_graph'range loop
      bar_graph(led) <= not led_on when bcd > bar_graph'length else
                        led_on when led < bcd else
                        not led_on;
    end loop;
  end process led_driver;
end architecture rtl;

【讨论】：