Verilog 二进制编码的十进制加法器未正确输出

Question

我是 Verilog 的新手，基本上是在尝试自学一个用于大学的数字逻辑设计模块。我正在尝试使用两个全加器在 Verilog 中编写 BCD 加法器，中间有一些逻辑，以便在需要时转换为 BCD。

这是我的代码：

module      binary_adder (
    output  [3:0]   Sum,
    output          C_out,
    input   [3:0]   A, B,
    input           C_in
);
    assign  {C_out, Sum} = A || B || C_in;
endmodule

module      BCD_Adder (
    output  [3:0]   Sum,
    output          Carry_out,
    input   [3:0]   Addend, Augend,
    input           Carry_in
);

wire [3:0]  Z, correction;
wire adder1C_out, carryInAdder2, adder2C_out;

    binary_adder adder1 (.Sum(Z), .C_out(adder1C_out), .A(Addend), .B(Augend), .C_in(Carry_in));
    
assign Carry_out = (adder1C_out || (Z[3] && Z[1]) || (Z[3] && Z[2]));
assign correction = (Carry_out) ? (4'b0110) : (4'b0000);
assign carryInAdder2 = (1'b0);

    binary_adder adder2 (.Sum(Sum), .C_out(adder2C_out), .A(correction), .B(Z), .C_in(carryInAdder2));

endmodule

出于某种原因，我不断收到以下输出：

已提交：A = 0000，B = 0010，进位 = 0，总和 = 0001，进位 = 0

预期：A = 0000，B = 0010，进位 = 0，总和 = 0010，进位 = 0

已提交：A = 0000，B = 0011，进位 = 0，总和 = 0001，进位 = 0

预期：A = 0000，B = 0011，进位 = 0，总和 = 0011，进位 = 0

已提交：A = 0000，B = 0100，进位 = 0，总和 = 0001，进位 = 0

预期：A = 0000，B = 0100，进位 = 0，总和 = 0100，进位 = 0

对于所有值，它基本上都是这样继续的。我的 A、B、进位和进位值始终匹配，但由于某种原因，输出总和始终为 0001。我不确定我哪里出错了，逻辑对我来说似乎没问题。我对此很陌生，只知道基础知识，因此将不胜感激！

谢谢， 韦斯

Answer 1

binary_adder中的逻辑没有实现加法；按照目前的写法，如果A、B 或C_in 中的任何一个不为零，它只会将Sum 设置为1。

虽然有许多多位加法架构（请参阅https://en.wikipedia.org/wiki/Adder_(electronics)#Adders_supporting_multiple_bits），但最容易理解的是波纹进位加法器。它实现了几个全加器并将它们链接在一起以实现加法。

此架构的简单实现如下所示：

module full_add(input A, B, Cin,
                output S, Cout);
  // Basic implementation of a Full Adder (see https://en.wikipedia.org/wiki/Adder_(electronics)#Full_adder)
  assign S = A ^ B ^ Cin;
  assign Cout = A & B | ((A ^ B) & Cin); // Note I use bit-wise operators like | and ^ instead of logical ones like ||; its important to know the difference
endmodule

module add(input [3:0] A, B,
           input Cin,
           output [3:0] S,
           output Cout);

  wire [3:0] Carries; // Internal wires for the carries between full adders in Ripple Carry

  // This is an array instance which just makes [3:0], ie 4, instances of the full adder.
  // Take note that a single Full Adder modules takes in single bits, but here
  // I can pass bit vectors like A ([3:0]) directly which assign full_add[0].A = A[0], full_add[1].A = A[1], etc
  // Common alternatives to using array instances (which are more rare) include generate statements or just instantiate the module X times
  full_add f[3:0](.A(A), .B(B), .Cin({Carries[2:0], Cin}), .S(S), .Cout(Carries));

  assign Cout = Carries[3];
endmodule