For循环中的VHDL错误

Question

在以下代码中，我收到以下错误，但我不明白为什么会出现错误。

library ieee;
use ieee.std_logic_1164.all;

entity RGSTR_SHFT_N_PARAL_B2 is

Generic (
     n: integer := 4  
     );

  port(
    DATA : in std_logic_vector((n-1) downto 0); 
    Shift_In : in std_logic; 
    Load : in std_logic;  
    Enable : in std_logic;  
CLK : in    std_logic;  
S : out   std_logic_vector((n-1) downto 0)   
        );
end entity RGSTR_SHFT_N_PARAL_B2;

architecture simple of RGSTR_SHFT_N_PARAL_B2 is

  signal temp_S: std_logic_vector((n-1) downto 0);

  signal LOW0, HIGH1: std_logic; -- Constant Signals   

  -- Use the D flip flop of B1 excersise
      component D_FF_B1 is
        port( 
        Enable      : in    std_logic;  
       Load        : in std_logic;  
    Load_Val    : in    std_logic;  
     Data_in     : in   std_logic;  
     CLK        : in    std_logic;  
     Q           : out   std_logic  
    );
  end component;

begin

  p0:process(Enable, CLK) is
  begin

-- Initialisations 

  LOW0  <= '0';
  HIGH1 <= '1';

    if (Enable = LOW0) then
           L0: for i in 0 to (n-1) loop
              temp_S(i) <= temp_S(i);
           end loop;
       elsif (CLK 'event and CLK = HIGH1) then 
           if (Load = LOW0)  then             -- Shifter is enabled
              L1: for i in 0 to (n-2) loop
                  temp_S(i) <= temp_S(i+1);
              end loop;
              temp_S(n-1) <= Shift_In;
           else                               -- Loader is enabled
              L2: for i in 0 to (n-1) loop
                X1: D_FF_B1 port map(HIGH1, LOW0, LOW0, DATA(i), CLK, temp_S(i));
              end loop;
           end if;
       end if;

  L3: for i in 0 to (n-1) loop
     S(i) <= temp_S(i);
  end loop;

  end process p0;

end architecture simple;

错误信息：

Error (10500): VHDL syntax error at RGSTR_SHFT_N_PARAL_B2.vhd(79) near text "port";  expecting "(", or "'", or "."
Error (10500): VHDL syntax error at RGSTR_SHFT_N_PARAL_B2.vhd(79) near text ";";  expecting ":=", or "<="

我用 Quartus II 编译 VHDL 程序。

Answer 1

process 中的模块实例化不是合法的 VHDL 语法，如下所示：

p0:process(Enable, CLK) is
begin
...
  L2: for i in 0 to (n-1) loop
    X1: D_FF_B1 port map(HIGH1, LOW0, LOW0, DATA(i), CLK, temp_S(i));
  end loop;
...
end process p0;

模块的实例化必须作为process之外的并发语句来完成。

根据代码，似乎可以移动模块实例化 在process 之外，代码类似于：

signal temp_S_x1 : std_logic_vector((n-1) downto 0);
...
L2 : for i in 0 to (n-1) generate
  X1 : D_FF_B1 port map(HIGH1, LOW0, LOW0, DATA(i), CLK, temp_S_x1(i));
end generate;
...
p0 : process(Enable, CLK) is
  ...
  L2: for i in 0 to (n-1) loop
    temp_S(n-1) <= temp_S_x1(i);
  end loop;

请注意，您应该使用constant 声明常量LOW0 和HIGH1 而不是signal，然后删除LOW0和HIGH1在p0process中赋值：

constant LOW0 : std_logic := '0';
constant HIGH1 : std_logic := '1';

或者直接使用 '0' 和 '1' 而不是声明任何常量。

另请注意，p0 process 不是格式正确的翻转过程 失败，所以你会从 Quartus 收到一些额外的警告，因为缺少 temp_S 灵敏度列表中的信号。如果Enable被同步使用，那么 使用如下模板：

p0 : process(Enable, CLK) is
begin
  if rising_edge(CLK) then
    if (Enable = '0') then