如何使用 Verilog 将 16 * 2 LCD(HD44780) 连接到 FPGA/CPLD？

Question

我想使用 Verilog HDL 将16 character * 2 line LCD (HD44780) 连接到我的 FPGA 板。我写的程序根本不起作用，我不知道为什么，即使我做了一个状态机并插入了延迟。请注意，我使用的是 8 位模式。这是我的代码：

module lcd(input wire clk,output reg [7:0]data,output reg rs,output reg rw ,output reg enb);        
wire sclk;//Slow Clock for Giving 450 ns Wide Delay
reg [3:0]state=4'b0000;
reg [3:0]next_state;
sender send(clk,sclk);  //Instance of Counter For Generating Delay

always@(sclk)
begin
state=next_state;
end

//Always First Block thant Handles flow of Our state machines means Always Second block//
//Always Second Block For State Machine of Our 16 * 2 LCD///////////////////////////////    

always@(state)
begin
////////////////These State are For LCD Commands////////////////
enb=1'b0;

case(state)

4'b0000:begin    //Do Noting because this state waste in Initialization of "state" variable..
next_state=4'b0001;
end         


4'b0001:begin    //Using LCD Command 0X38(00111000)
rs=1'b0;
rw=1'b0;
data=8'b00111000;
enb=1'b1; //Logic is Sending High(1) then uses clocks Delay then Low(0) of Next state..
next_state=4'b0010;
end      

4'b0010:begin   //Using LCD Command 0X0E(00001110)
rs=1'b0;
rw=1'b0;
data=8'b00001110;   
enb=1'b1; //Logic is Sending High(1) then uses clocks Delay then Low(0) of Next state..
next_state=4'b0011;
end


4'b0011:begin   //Using LCD Command 0X01(00000001)
rs=1'b0;
rw=1'b0;
data=8'b00000001;   
enb=1'b1; //Logic is Sending High(1) then uses clocks Delay then Low(0) of Next state..
next_state=4'b0100;
end

4'b0100:begin   //Using LCD Command 0X06(00000110)
rs=1'b0;
rw=1'b0;
data=8'b00000110;
enb=1'b1; //Logic is Sending High(1) then uses clocks Delay then Low(0) of Next state..
next_state=4'b0110; 
end



////////////These State Are for LCD Data////////////////////

4'b0110:begin    //Using LCD "S" Having Value
rs=1'b1;
rw=1'b0;
data=8'b01010111;
enb=1'b1; //Logic is Sending High(1) then uses clocks Delay then Low(0) of Next state..
next_state=4'b0110;
end




endcase
end


endmodule

这是其实例“Sender”的代码：

module sender(input wire clkin,output reg clkout);
 reg [19:0]tmp=20'b00000_00000_00000_00000;

//Always Block for Greater than 450ns wide delay Generation////////

always@(posedge clkin)
 begin 
  tmp = tmp+1'b1;
  clkout=tmp[19]; 
 end        

 endmodule

请在您的板上检查此代码。我在我的“DIGIASIC Altera Cyclone II 板”上进行了尝试，它有一个EP2C8Q208C8 fpga。我还尝试了在发送方实例中越来越低的延迟，但都没有奏效。

Answer 1

时间要求比您在代码中实现的要多得多。您需要仔细查看 LCD 模块的数据表。请注意，LCD 模块执行命令需要很多 微秒...您的 450 ns 延迟还不够。