VHDL 方法调用

Question

是否可以编写一个代码段并调用它，而不是多次编写该段？ IE。我想复用一段代码如下图：

process (currentState)
begin
    case currentState is
    when requiredCoinsTensAnode => anodes <= "100000";--turn on the tens display
        case tensCount is
        when "0000" => segDisplay <= "1111110"; --0
        when "0001" => segDisplay <= "0110000"; --1
        when "0010" => segDisplay <= "1101101"; --2
        when "0011" => segDisplay <= "1111001"; --3
        when "0100" => segDisplay <= "0110011"; --4
        when "0101" => segDisplay <= "1011011"; --5
        when "0110" => segDisplay <= "1011111"; --6
        when "0111" => segDisplay <= "1110000"; --7
        when "1000" => segDisplay <= "1111111"; --8
        when others => segDisplay <= "1111011"; --9
        end case;
        nextState <= requiredCoinsUnitsAnode;--just displayed the tens digit, next we need to display the units digit
    when requiredCoinsUnitsAnode => anodes <= "010000";--turn on the units display
        case unitsCount is
        when "0000" => segDisplay <= "1111110"; --0
        when "0001" => segDisplay <= "0110000"; --1
        when "0010" => segDisplay <= "1101101"; --2
        when "0011" => segDisplay <= "1111001"; --3
        when "0100" => segDisplay <= "0110011"; --4
        when "0101" => segDisplay <= "1011011"; --5
        when "0110" => segDisplay <= "1011111"; --6
        when "0111" => segDisplay <= "1110000"; --7
        when "1000" => segDisplay <= "1111111"; --8
        when others => segDisplay <= "1111011"; --9
        end case;
        nextState <= insertedCoinsTensAnode;
    end case;
end process;

Answer 1

正如 ravi 所指出的，函数是一种选择。

function f_segDisplay (
  signal segCount : std_logic_vector(6 downto 0))
  return std_logic_vector(3 downto 0) is
begin  -- f_segDisplay
    case segCount is
      when "0000" => return "1111110";  --0
      when "0001" => return "0110000";  --1
      when "0010" => return "1101101";  --2
      when "0011" => return "1111001";  --3
      when "0100" => return "0110011";  --4
      when "0101" => return "1011011";  --5
      when "0110" => return "1011111";  --6
      when "0111" => return "1110000";  --7
      when "1000" => return "1111111";  --8
      when others => return "1111011";  --9
    end case;
end f_segDisplay;

process (currentState, tensCount, unitsCount)
begin
  case currentState is
    when requiredCoinsTensAnode =>
      anodes     <= "100000";          --turn on the tens display
      segDisplay <= f_segDisplay(tensCount);
      nextState  <= requiredCoinsUnitsAnode;
    when requiredCoinsUnitsAnode =>
      anodes     <= "010000";          --turn on the units display
      segDisplay <= f_segDisplay(unitsCount);
      nextState  <= insertedCoinsTensAnode;
  end case;
end process;

根据编译器和选项，它可能决定将函数代码内嵌。这将导致放置多个逻辑实例，就像您的原始代码一样。

另一种方法是将公共代码取出到另一个进程中：

p_segdisplay : process (segCount)
begin  -- process p_segdisplay
  case segCount is
    when "0000" => segDisplay <= "1111110";  --0
    when "0001" => segDisplay <= "0110000";  --1
    when "0010" => segDisplay <= "1101101";  --2
    when "0011" => segDisplay <= "1111001";  --3
    when "0100" => segDisplay <= "0110011";  --4
    when "0101" => segDisplay <= "1011011";  --5
    when "0110" => segDisplay <= "1011111";  --6
    when "0111" => segDisplay <= "1110000";  --7
    when "1000" => segDisplay <= "1111111";  --8
    when others => segDisplay <= "1111011";  --9
  end case;
end process p_segdisplay;

process (currentState, tensCount, unitsCount)
begin
  case currentState is
    when requiredCoinsTensAnode =>
      anodes    <= "100000";          --turn on the tens display
      segCount  <= tensCount;
      nextState <= requiredCoinsUnitsAnode;
    when requiredCoinsUnitsAnode =>
      anodes    <= "010000";          --turn on the units display
      segCount  <= unitsCount;
      nextState <= insertedCoinsTensAnode;
  end case;
end process;

顺便说一句：您的敏感度列表中需要 tensCount 和 unitsCount。

在进行面积或功耗意识设计时，像这样抽象公共资源是一种有用的技术。

两者应该以相同的方式工作，完美的工具会从两者中产生相同的逻辑，但我们很少有完美的工具。尝试不同的风格。有些在某些工具上产生更好的结果，有些在其他工具上产生更好的结果。

Answer 2

是的，您可以使用 VHDL 中的函数。

查看http://www.csee.umbc.edu/portal/help/VHDL/design.html#funcd
http://www.pldworld.com/_hdl/1/www.ireste.fr/fdl/vcl/lesd/les_3.htm

Answer 3

该代码在function 或procedure 中可能是最好的。

entity 是在 VHDL 中封装代码的另一种方式。