如何在 VHDL 中使用 D 触发器在计数器构建中延迟复位信号？答案

【问题标题】：How to delay the reset signal in a counter build with D flip-flops in VHDL?如何在 VHDL 中使用 D 触发器在计数器构建中延迟复位信号？
【发布时间】：2016-12-14 20:24:02
【问题描述】：

我正在尝试使用 sn7493 计数器构建模 25 计数器。我已经对自己的 D 触发器进行了建模，并使用它们来重新创建计数器的内部结构。它可以工作，直到需要重置。在“24”之后，我得到“2”而不是“0”。我猜复位信号太短，无法正确复位，但我不知道如何让它更长。

--DFF model
LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY D IS
PORT(
    Din, CLK, RES :IN std_logic;
    Q :OUT std_logic
);
END D;

ARCHITECTURE behavior of D IS
begin 
PROCESS(CLK)
    begin
        if rising_edge(CLK) then
            Q <= Din;
        end if;
        if (RES='0') then
            Q <= '0';
        end if;
    end PROCESS;
END behavior;


--SN7493 counter model
LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY c7493 IS
PORT (
    CLKA,CLKB,R1,R2: IN std_logic;
    Q: INOUT std_logic_vector(0 to 3)
);
END c7493;

ARCHITECTURE behavior of c7493 IS

    COMPONENT D IS
    PORT(
        Din, CLK, RES :IN std_logic;
        Q :OUT std_logic
    );
END COMPONENT D;

signal A_out,B_out,C_out,D_out: std_logic;
BEGIN
    DA: D PORT MAP(
        Din => not A_out,
        CLK => not CLKA,
        RES =>R1 nand R2,
        Q => A_out
    );
    DB: D PORT MAP(
        Din => not B_out,
        CLK => not CLKB,
        RES => R1 nand R2,
        Q => B_out
    );
    DC: D PORT MAP(
        Din => B_out xor C_out,
        CLK => not CLKB,
        RES =>R1 nand R2,
        Q => C_out
    );
    DD: D PORT MAP(
        Din => (B_out and C_out) xor D_out,
        CLK => not CLKB,
        RES =>R1 nand R2,
        Q => D_out
    );
    Q(0) <=A_out;
    Q(1) <=B_out;
    Q(2) <=C_out;
    Q(3) <=D_out;

END behavior;


--main program
LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY plytka IS
PORT(
    SW: IN std_logic_vector(0 to 0);
    LEDR: OUT std_logic_vector (4 downto 0)
    );
END plytka;

ARCHITECTURE projekt OF plytka IS
COMPONENT c7493 IS
PORT(
    CLKA,CLKB,R1,R2: IN std_logic;
    Q: INOUT std_logic_vector(0 to 3)
);
END COMPONENT c7493;

signal A_out,B_out,C_out,D_out,E_out: std_logic;
BEGIN
    c7493A: c7493 PORT MAP(
        CLKA => SW(0),
        CLKB => A_out,
        R1 => (A_out and D_out and E_out),
        R2 => (A_out and D_out and E_out),
        Q(0) => A_out,
        Q(1) => B_out,
        Q(2) => C_out,
        Q(3) => D_out
    );
    c7493B: c7493 PORT MAP(
        CLKA => A_out and B_out and C_out and D_out,
          CLKB => '0',
        R1 => (A_out and D_out and E_out),
        R2 => (A_out and D_out and E_out),
        Q(0) => E_out
    );

    LEDR <= (E_out,D_out,C_out,B_out,A_out);
END projekt;

【问题讨论】：

标签： vhdl counter reset

【解决方案1】：

一种简单的方法是在复位信号中创建一个小向量和时钟（假设同步复位！），然后检查它是否全为零......

std_logic_vector reset_vec : std_logic_vector(3 downto 0) := (others => '0');

-- Then in architecture body
reset_vec   <= reset_vec(2 downto 0) & reset when rising_edge(clk);
elong_reset <= '1' when reset_vec /= "0000" OR reset = '1' else '0';

祝你好运！

【讨论】：