如何在 VHDL 中测试矢量多路复用器的所有情况？答案

【问题标题】：How can I test all cases of vector multiplexer in VHDL?如何在 VHDL 中测试矢量多路复用器的所有情况？
【发布时间】：2020-05-07 07:01:40
【问题描述】：

这是我的第一个 VHDL 代码，我有这个多路复用器（两个输入，一个选择位），它具有 8 位向量输入。如何编写生成所有可能向量的测试函数？

library IEEE;
use IEEE.std_logic_1164.all;

entity mux is
port(
    in0, in1: in std_logic_vector(7 downto 0);
    sel: in std_logic;
    out0: out std_logic_vector(7 downto 0);
end mux;

architecture dataflow of mux is
begin
    out0<=in1 when sel='1'
    else in0;
end dataflow;

这是目前的测试平台：

library IEEE;
use IEEE.std_logic_1164.all;

entity testbench is --empty
end testbench;

architecture tb of testbench is

-- DuT component
component mux is
port(
    in0, in1: in std_logic_vector(7 downto 0); 
sel: in std_logic;
    out0: out std_logic);
end component;

signal tb_sel: std_logic;
signal tb_in0, tb_in1, tb_out0: std_logic_vector(7 downto 0);

begin
-- Connect DuT
DuT: mux port map(tb_in0, tb_in1, tb_sel, tb_out0);

process
begin
    tb_sel <= 0;
    tb_in0 <= "00000000";
    tb_in1 <= "00000000";

    -- TODO: test all possibilities


    end process;
end tb;

【问题讨论】：

标签： vector vhdl test-bench

【解决方案1】：

可以使用这样的东西：

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;

entity testbench is --empty
end testbench;

architecture tb of testbench is

signal tb_sel: std_logic;
signal tb_in0, tb_in1, tb_out0: std_logic_vector(7 downto 0);

begin
-- Connect DuT

  DuT: entity work.mux port map(tb_in0, tb_in1, tb_sel, tb_out0);

process
begin
    -- Done: Test all possibilities

    for sel in 0 to 1 loop
      for in0 in 0 to 2 ** tb_in0'length - 1 loop
        for in1 in 0 to 2 ** tb_in1'length - 1 loop
          -- Make stimuli
          if sel = 0 then
            tb_sel <= '0';
          else
            tb_sel <= '1';
          end if;
          tb_in0 <= std_logic_vector(to_unsigned(in0, tb_in0'length));
          tb_in1 <= std_logic_vector(to_unsigned(in1, tb_in1'length));
          -- Wait for output, also to ease viewing in waveforms
          wait for 10 ns;
          -- Test output
          if sel = 0 then
            assert tb_out0 = tb_in0 report "Wrong out0 output value for selected in0 input" severity error;
          else
            assert tb_out0 = tb_in1 report "Wrong out0 output value for selected in1 input" severity error;
          end if;
        end loop;
      end loop;
    end loop;

    report "OK   (not actual failure)" severity FAILURE;
    wait;

    end process;
end tb;

请注意，我使用了多路复用的实体实例化，以避免组件声明，端口列表中实际上存在错误；清楚地表明为什么写两次相同的东西是个坏主意;-)

我也没有包含 IEEE numeric_std 包。

在 X 值的测试方面当然也可以改进，但是对于像 mux 这样的简单模块，上面的测试将提供所需的覆盖率。

如需更高级的测试，请查看OSVVM。

【讨论】：