【问题标题】:VHDL AND operator usage " no function declarations for operator "and""VHDL AND 运算符用法“无运算符“和”的函数声明
【发布时间】:2021-12-11 19:36:03
【问题描述】:

我有以下代码:

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;

ENTITY hazard_unit_forwards IS
    PORT (
        i_Rs1E, i_Rs2E : IN STD_LOGIC_VECTOR(4 downto 0);
        i_RdM, i_RdW : IN STD_LOGIC_VECTOR(4 downto 0);
        i_RegWriteM, i_RegWriteW : IN STD_LOGIC;
        o_ForwardAE, o_ForwardBE : OUT STD_LOGIC_VECTOR(1 downto 0)         -- forward A and B to execute stage
    );
END;

ARCHITECTURE behave OF hazard_unit_forwards IS

BEGIN
    -- forwarding logic for Rs1E
    PROCESS(i_Rs1E, i_RdM, i_RdW, i_RegWriteM, i_RegWriteW) BEGIN
        IF(((i_Rs1E = i_RdM) AND i_RegWriteM) AND (i_Rs1E /= "00000")) THEN     -- forward from memory stage
            o_ForwardAE <= "10";
        ELSIF (((i_Rs1E = i_RdW) AND i_RegWriteW) AND (i_Rs1E /= "00000")) THEN -- forward from writeback stage
            o_ForwardAE <= "01";
        ELSE                -- no forwarding (use RF output)
            o_ForwardAE <= "00";
        END IF;
    END PROCESS;
    
    -- forwarding logic for Rs2E
    PROCESS(i_Rs2E, i_RdM, i_RdW, i_RegWriteM, i_RegWriteW) BEGIN
        IF(((i_Rs2E = i_RdM) AND i_RegWriteM) AND (i_Rs2E /= "00000")) THEN     -- forward from memory stage
            o_ForwardBE <= "10";
        ELSIF (((i_Rs2E = i_RdW) AND i_RegWriteW) AND (i_Rs2E /= "00000")) THEN -- forward from writeback stage
            o_ForwardBE <= "01";
        ELSE                -- no forwarding (use RF output)
            o_ForwardBE <= "00";
        END IF;
    END PROCESS;
END;

VHDL 类型给了我一个 PTSD,我确信这是类型的问题,但不知道哪里出了问题。

GHDL 给我以下错误:

hazard_unit_forwards.vhd:20:37:error: no function declarations for operator "and"
hazard_unit_forwards.vhd:22:41:error: no function declarations for operator "and"
hazard_unit_forwards.vhd:31:37:error: no function declarations for operator "and"
hazard_unit_forwards.vhd:33:41:error: no function declarations for operator "and"

那么,怎么了?

(代码中基本上到处都是AND操作符)

【问题讨论】:

  • 那么,怎么了? (i_Rs1E = i_RdM) AND i_RegWriteM- 和逻辑运算符的两个操作数不是同一类型。左边的操作数是一个布尔值。右手操作数是 std_logic。请参阅 IEEE Std 1076-2008 9.2.2 逻辑运算符。

标签: vhdl ghdl


【解决方案1】:

你可以像这样改变 If 语句:

 (((i_Rs1E = i_RdM) AND (i_RegWriteM = '1') AND (i_Rs1E /= "00000"))

我希望这对你有用。

【讨论】:

  • 您在答案中显示的表达式是一个条件(返回一个布尔值)。有趣的是,您的条件中没有任何括号(((i_Rs1E = i_RdM) AND (i_RegWriteM = '1') AND (i_Rs1E /= "00000")) 是必需的,因为关系运算符的优先级高于逻辑运算符。
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