【发布时间】：2020-05-03 17:15:33
【问题描述】：
我正在尝试运行测试台，但当我尝试运行模拟时，我收到以下错误：
./rc_symbols_testbench:error: 事务不是升序
./rc_symbols_testbench:error: 模拟失败 msf_symbols.vhd rc_symbols_testbench.vhd
仍然产生错误的测试台的简化版本：
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use STD.textio.all;
use IEEE.std_logic_textio.all;
entity rc_symbols_testbench is
end;
architecture impl of rc_symbols_testbench is
subtype byte is std_logic_vector(7 downto 0);
constant byte_null: byte := (others => '0');
constant byte_unknown: byte := (others => 'X');
constant clk_freq: integer := 25500;
constant clk_period: time := (1 / (clk_freq))*sec;
constant gate_delay: time := 0.1 ns;
constant t_sample: time := 100 ms;
signal eod: std_logic := '0';
signal clk: std_logic := '0';
signal rst: std_logic := '0';
signal dcf_tro: std_logic := '0';
begin
process
begin
while eod = '0' loop
clk <= not clk;
--wait for clk_period / 2;
wait for 19.60784314 us; --19.6us approx = clock period / 2
end loop;
wait;
end process;
rst <= '1', '0' after 150 ms;
process
file data_file: text;
variable data_line: line;
variable dcf_do_var: byte;
variable dcf_tro_var: std_logic;
variable dcf_so_var: std_logic;
variable msf_do_var: byte;
variable msf_tro_var: std_logic;
variable msf_so_var: std_logic;
variable t_var: time;
begin
file_open(data_file, "rc_symbols.dat", read_mode);
while not endfile(data_file) loop
readline(data_file, data_line);
hread(data_line, dcf_do_var);
read(data_line, dcf_so_var);
read(data_line, dcf_tro_var);
hread(data_line, msf_do_var);
read(data_line, msf_so_var);
read(data_line, msf_tro_var);
read(data_line, t_var);
if t_var > now then
wait for t_var - now;
end if;
dcf_tro <= dcf_tro_var, '0' after clk_period;
end loop;
file_close(data_file);
eod <= '1';
wait;
end process;
end;
我还将rc_symbols.dat 简化为：
00 0 0 FF 0 1 1736901.960861734 us
00 0 0 FF 0 0 1736941.176548008 us
0C 0 1 FF 0 0 1754705.88243013 us
0C 0 0 FF 0 0 1754745.098116404 us
0C 0 0 31 0 1 1837019.607919256 us
0C 0 0 31 0 0 1837058.82360553 us
00 0 1 31 0 0 1854823.529487652 us
00 0 0 31 0 0 1854862.745173926 us
00 0 0 00 0 1 1937137.254976778 us
00 0 0 00 0 0 1937176.470663052 us
00 0 1 00 0 0 1954901.9608589 us
00 0 0 00 0 0 1954941.176545174 us
00 0 0 00 0 1 2037215.686348026 us
00 0 0 00 0 0 2037254.9020343 us
00 0 1 00 0 0 2055019.607916422 us
00 0 0 00 0 0 2055058.823602696 us
00 0 0 00 0 1 2137333.333405548 us
00 0 0 00 0 0 2137372.549091822 us
00 0 1 00 0 0 2155137.254973944 us
在我看来，一切都是按升序排列的，所以我仍然不确定。
如果我注释掉它，它会模拟，但我不确定如何修复错误：
dcf_tro <= dcf_tro_var, '0' after clk_period;
【问题讨论】：
-
Any ideas what else could be causing this problem?是的。 （是/否问题对未来的读者可能毫无用处，请提供minimal reproducible example）。./rc_symbols_testbench:error: transactions not in ascending order- 在执行信号分配时出现在您的测试台中。事务由当前或未来的驱动程序值和时间（没有 after 时间表达式的当前模拟时间）组成，参见 IEEE 1076-2008 10.5.2.2 Executing a simple assignment statement para 6 “这是一个错误如果新事务的序列不是按时间升序排列的。”，14.7.2 驱动程序。 -
@user1155120 所以你认为我在关注
Makefile时看错了？此外，“知道还有什么可能导致这种情况”在实际意义上并不是一个是/否的问题......不过我会改写它 -
@user1155120 我还添加了一些信息，鉴于您所说的这些信息可能更相关
-
是的。你是
looking at the wrong thing when getting concerned with the Makefile。这是在仿真过程中检测到的 VHDL 语义错误。提供minimal reproducible example，您的编辑还不够...... -
@user1155120 我已经从测试平台中删除了所有不相关的内容，并发布了尽可能接近 MRE 的内容。感谢您抽出宝贵时间提供帮助
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