【发布时间】：2021-09-15 12:32:48
【问题描述】：
我在 Quartus Lite Edition 中偶然发现了一个非常奇怪的行为。我正在使用带有 Cyclone IV FPGA 的 DE2-115 板为大学项目设置开发容器。
使用 Quartus 19.1 一切构建良好并且按预期工作，但如果我使用 20.1 版本，我发现装配工需要 17 分钟而不是 8 秒。
比较日志时，引起我注意的是，使用的资源从 18897 个逻辑单元增加到 118824 个逻辑单元，但 RAM 段从 322 个减少到 190 个。资源量较高可能是拟合和路由过程需要 17 分钟。
有没有人遇到过类似的行为？有什么我应该激活/停用的吗？
综合日志输出 Quartus 19.1
...
[0m[0;32mInfo (128003): Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 745 ps
[0m[0;32mInfo (128001): Physical synthesis optimizations for speed complete: elapsed time is 00:00:07
[0m[0;32mInfo (16010): Generating hard_block partition "hard_block:auto_generated_inst"
[0m[0;32m Info (16011): Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL
[0m[0;32mInfo (21057): Implemented 19285 device resources after synthesis - the final resource count might be different
[0m[0;32m Info (21058): Implemented 6 input pins
[0m[0;32m Info (21059): Implemented 35 output pins
[0m[0;32m Info (21060): Implemented 16 bidirectional pins
[0m[0;32m Info (21061): Implemented 18897 logic cells
[0m[0;32m Info (21064): Implemented 322 RAM segments
[0m[0;32m Info (21065): Implemented 1 PLLs
[0m[0;32m Info (21062): Implemented 8 DSP elements
[0m[0;32mInfo: Quartus Prime Analysis & Synthesis was successful. 0 errors, 33 warnings
[0m[0;32m Info: Peak virtual memory: 1337 megabytes
[0m[0;32m Info: Processing ended: Wed Sep 15 08:32:55 2021
[0m[0;32m Info: Elapsed time: 00:01:04
[0m[0;32m Info: Total CPU time (on all processors): 00:01:13
...
综合日志输出 Quartus 20.1
...
[0m[0;32mInfo (128003): Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 330 ps
[0m[0;32mInfo (128001): Physical synthesis optimizations for speed complete: elapsed time is 00:00:27
[0m[0;32mInfo (16010): Generating hard_block partition "hard_block:auto_generated_inst"
[0m[0;32m Info (16011): Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL
[0m[0;32mInfo (21057): Implemented 119080 device resources after synthesis - the final resource count might be different
[0m[0;32m Info (21058): Implemented 6 input pins
[0m[0;32m Info (21059): Implemented 35 output pins
[0m[0;32m Info (21060): Implemented 16 bidirectional pins
[0m[0;32m Info (21061): Implemented 118824 logic cells
[0m[0;32m Info (21064): Implemented 190 RAM segments
[0m[0;32m Info (21065): Implemented 1 PLLs
[0m[0;32m Info (21062): Implemented 8 DSP elements
[0m[0;32mInfo: Quartus Prime Analysis & Synthesis was successful. 0 errors, 25 warnings
[0m[0;32m Info: Peak virtual memory: 1181 megabytes
[0m[0;32m Info: Processing ended: Wed Sep 15 09:49:49 2021
[0m[0;32m Info: Elapsed time: 00:02:48
[0m[0;32m Info: Total CPU time (on all processors): 00:02:57
...
完整日志：
https://github.com/t-crest/patmos/files/7169188/build_log_quartus_20.1.log
https://github.com/t-crest/patmos/files/7169189/build_log_quartus_19.1.log
【问题讨论】：
-
Found 12 instances of uninferred RAM logic和... is uninferred due to asynchronous read logic。应该是这样的：intel.com/content/www/us/en/support/programmable/articles/… -
不知道为什么 quartus 19 设法通过添加传递逻辑来克服这个问题。是关于编译器选项，还是因为在两个（？）项目中定义不同的某些变量而导致设计具有不同的行为，不知道......
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AFAIK 现在定义了可以改变行为的变量。默认值已更改，或者他们更改了编译器中的某些内容，从而破坏了代码。
标签： fpga quartus intel-fpga