【发布时间】：2021-05-19 08:29:21
【问题描述】：
所以这是我的 Problem Statement 洗衣机代码。
我已经完全按照给定的规范编写了模块，但我对 100 个时钟周期或 50 个时钟周期感到震惊。
我不知道如何让代码停在那里并等待 100 个时钟周期或 50 个时钟周期执行，在时钟周期执行期间对输出没有影响。
module Washing_Machine(clk,power,water_full,detergent_full,spin_dry,wash_ongoing,spindry_ongoing,state0,state1);
input clk,water_full,detergent_full,spin_dry;
input power;
output reg wash_ongoing,spindry_ongoing;
output reg state0;
output reg state1;
always @ (posedge clk)
begin
if(power == 1'b0)
begin
wash_ongoing = 1'b0;
spindry_ongoing = 1'b0;
//idle state
state0 = 1'bx;
state1 = 1'bx;
end
else if(power == 1'b1)
begin
case ({spin_dry,water_full,detergent_full})
3'b000 : begin
//water state and waits for water full.
wash_ongoing = 1'b0;
spindry_ongoing = 1'b0;
// water state
state0 = 1'b0;
state1 = 1'b0;
end
3'b010 : begin
// water state and water full = 1 and
//goes to detergent state
wash_ongoing = 1'b0;
spindry_ongoing = 1'b0;
//detergent state
state0 = 1'b0;
state1 = 1'b1;
end
3'b011 : begin
// detergent state and detergent full = 1 and
//goes to wash state and assigns
wash_ongoing = 1'b1;
spindry_ongoing = 1'b0;
//wash state
state0 = 1'b1;
state1 = 1'b0;
// now it waits for 100 clock cycles.....
**I am struck here**
//after
wash_ongoing = 1'b0;
// spin dry state
state0 = 1'b1;
state1 = 1'b1;
//assigns
spindry_ongoing = 1'b1;
wash_ongoing = 1'b0;
// after 50 clock cycles.....
// assigns
spindry_ongoing = 1'b0;
// idle state
state0 = 1'bx;
state1 = 1'bx;
end
3'b100 , 3'b101 , 3'b110 , 3'b111 :
begin
// directly goes to spin dry state
// spin dry state
state0 = 1'b1;
state1 = 1'b1;
//assigns
spindry_ongoing = 1'b1;
wash_ongoing = 1'b0;
// after 50 clock cycles....
// assigns
spindry_ongoing = 1'b0;
// idle state
state0 = 1'bx;
state1 = 1'bx;
end
endcase
end
end
endmodule
【问题讨论】：
标签： verilog system-verilog icarus