我究竟做错了什么？测试台未正确更新答案

【问题标题】：What am I doing wrong? Testbench not updating correctly我究竟做错了什么？测试台未正确更新
【发布时间】：2021-03-18 21:15:22
【问题描述】：

我正在尝试实现测试台，以便在 3 个滴答声后，每个输入都会获得新的指定值。例如，前 3 秒（或滴答声）A = 10，B = 0，然后接下来的 3 秒（3 秒到 6 秒）A = 10，B = 16 等等。但是，在我的实际测试台上，值没有按照我想要的方式更新。我的语法错了吗？

这是我得到的当前值的屏幕截图。我在顶部画了红线代表每 3 个刻度。

https://gyazo.com/f2c0cddc192d0d6734c98334cd377f12

module ALU_tb();

reg [63:0] A, B;
reg [4:0] FS;
reg cin;

wire cout;
wire [63:0] result;
wire [3:0] status;


     
     Final_ALU dut (
     .A(A),
     .B(B),
     .FS(FS),
     .cin(cin),
     .cout(cout),
     .result(result),
     .status(status)
                    );

initial begin //A+1 //A=10 B=0
A <= 64'b0000000000000000000000000000000000000000000000000000000000001010;
B <= 64'b0000000000000000000000000000000000000000000000000000000000000000;
FS <= 5'b01000;
cin <= 1'b1;
end

always begin //A+B //A=10 B=16
#3
A <= 64'b0000000000000000000000000000000000000000000000000000000000001010;
B <= 64'b0000000000000000000000000000000000000000000000000000000000010000;
FS <= 5'b01000;
cin <= 1'd0;
#3;
end

always begin //A-B //A=10 B=16
#6
A <= 64'b0000000000000000000000000000000000000000000000000000000000001010;
B <= 64'b0000000000000000000000000000000000000000000000000000000000010000;
FS <= 5'b01001;
cin <= 1'd1;
#6; 
end

always begin //A-1 //A=10 , B=1
#9
A <= 64'b0000000000000000000000000000000000000000000000000000000000001010;
B <= 64'b0000000000000000000000000000000000000000000000000000000000000001;
FS <= 5'b01001;
cin <= 1'd1;
#9; 
end

always begin //-A //A=10 , B=0 (just twos complement of A)
#12
A <= 64'b0000000000000000000000000000000000000000000000000000000000001010;
B <= 64'b0000000000000000000000000000000000000000000000000000000000000000;
FS <= 5'b01010;
cin <= 1'd1;
#12; 
end


initial begin
#30 $finish;
end
endmodule

【问题讨论】：

标签： verilog fpga quartus intel-fpga

【解决方案1】：

您不应该对来自多个 always 块的同一信号进行分配。

解决此问题的一种方法是在initial 块内使用fork/join，并去掉always 关键字。这将对您的代码进行最小的更改：

initial begin
    fork
        begin //A+1 //A=10 B=0
        A <= 64'b0000000000000000000000000000000000000000000000000000000000001010;
        B <= 64'b0000000000000000000000000000000000000000000000000000000000000000;
        FS <= 5'b01000;
        cin <= 1'b1;
        end

        begin //A+B //A=10 B=16
        #3
        A <= 64'b0000000000000000000000000000000000000000000000000000000000001010;
        B <= 64'b0000000000000000000000000000000000000000000000000000000000010000;
        FS <= 5'b01000;
        cin <= 1'd0;
        #3;
        end

        begin //A-B //A=10 B=16
        #6
        A <= 64'b0000000000000000000000000000000000000000000000000000000000001010;
        B <= 64'b0000000000000000000000000000000000000000000000000000000000010000;
        FS <= 5'b01001;
        cin <= 1'd1;
        #6; 
        end

        begin //A-1 //A=10 , B=1
        #9
        A <= 64'b0000000000000000000000000000000000000000000000000000000000001010;
        B <= 64'b0000000000000000000000000000000000000000000000000000000000000001;
        FS <= 5'b01001;
        cin <= 1'd1;
        #9; 
        end

        begin //-A //A=10 , B=0 (just twos complement of A)
        #12
        A <= 64'b0000000000000000000000000000000000000000000000000000000000001010;
        B <= 64'b0000000000000000000000000000000000000000000000000000000000000000;
        FS <= 5'b01010;
        cin <= 1'd1;
        #12; 
        end
    join
end

更传统的方法是去掉fork，只在initial 块内按顺序驱动所有信号组。然后你必须相应地调整你所有的 # 延迟。

【讨论】：