【发布时间】：2015-10-13 08:31:56
【问题描述】：
我的测试台中有 4 个 DAI 接口实例。我一直在用我创建的环境运行一些模拟，并且没有出现错误问题。但是，当我尝试将我的断言绑定到接口实例时，我收到与在配置数据库中设置接口相关的错误。下面的代码显示了我将接口添加到配置数据库的位置：
//------------------------------------------------------------------------------------------------------
//Create instances of the interface for inputs and outputs - note these instances are the same, but they
//are hooked up differently in the env level
//------------------------------------------------------------------------------------------------------
//Parallel Inputs - To be used for the input drivers, agents and monitors
dai_if #(.P_WD_DATA (P_WD_DATA ),
.P_CH_NUM_MAX (P_CH_NUM_MAX ),
.P_WD_OFFSET (P_WD_OFFSET ),
.P_WD_CH_NUM (P_WD_CH_NUM ),
.P_WD_FMT (P_WD_FMT ),
.P_WD_WL (P_WD_WL )
)
dai_par_ivif();
//Serial Inputs - To be used for the input drivers, agents and monitors
dai_if #(.P_WD_DATA (P_WD_DATA ),
.P_CH_NUM_MAX (P_CH_NUM_MAX ),
.P_WD_OFFSET (P_WD_OFFSET ),
.P_WD_CH_NUM (P_WD_CH_NUM ),
.P_WD_FMT (P_WD_FMT ),
.P_WD_WL (P_WD_WL )
)
dai_ser_ivif();
//Parallel Outputs - To be used for the output monitors and agents
dai_if #(.P_WD_DATA (P_WD_DATA ),
.P_CH_NUM_MAX (P_CH_NUM_MAX ),
.P_WD_OFFSET (P_WD_OFFSET ),
.P_WD_CH_NUM (P_WD_CH_NUM ),
.P_WD_FMT (P_WD_FMT ),
.P_WD_WL (P_WD_WL )
)
dai_par_ovif();
//Serial Outputs - To be used for the output monitors and agents
dai_if #(.P_WD_DATA (P_WD_DATA ),
.P_CH_NUM_MAX (P_CH_NUM_MAX ),
.P_WD_OFFSET (P_WD_OFFSET ),
.P_WD_CH_NUM (P_WD_CH_NUM ),
.P_WD_FMT (P_WD_FMT ),
.P_WD_WL (P_WD_WL )
)
dai_ser_ovif();
//------------------------------------------------------------------------------------------------------
//Set interfaces in the database with specific hierachical paths.
//------------------------------------------------------------------------------------------------------
initial begin
//------------------------------------------------------------------------------------------------------
//Set these unrequired signals to their default values.
//------------------------------------------------------------------------------------------------------
dft_latch_clk = 1'b1;
dft_latch_rst_an = 1'b1;
scan_mode = 1'b0;
scan_enable = 1'b0;
uvm_config_db#(virtual dai_if)::set(uvm_root::get(), "uvm_test_top.dai_env.dai_ag_in[0]*", "dai_vif", dai_ser_ivif);
uvm_config_db#(virtual dai_if)::set(uvm_root::get(), "uvm_test_top.dai_env.dai_ag_in[1]*", "dai_vif", dai_par_ivif);
uvm_config_db#(virtual dai_if)::set(uvm_root::get(), "uvm_test_top.dai_env.dai_ag_out[0]*", "dai_vif", dai_par_ovif);
uvm_config_db#(virtual dai_if)::set(uvm_root::get(), "uvm_test_top.dai_env.dai_ag_out[1]*", "dai_vif", dai_ser_ovif);
//Scoreboard interface uses the one which drives the clock
uvm_config_db#(virtual dai_if)::set(uvm_root::get(), "uvm_test_top.dai_env.dai_sb[0]*", "dai_vif", dai_ser_ivif);
uvm_config_db#(virtual dai_if)::set(uvm_root::get(), "uvm_test_top.dai_env.dai_sb[1]*", "dai_vif", dai_ser_ivif);
//Print top level topology
uvm_top.print();
//Run specific test using command line switch addition (+UVM_TESTNAME=test_name)
run_test();
end
我在顶层模块中绑定了endmodule之前的接口断言，如下所示：
bind dai_if :dai_ser_ivif dai_ser_in_checkers #(.P_WD_DATA (P_WD_DATA ),
.P_CH_NUM_MAX (P_CH_NUM_MAX ),
.P_WD_OFFSET (P_WD_OFFSET ),
.P_WD_CH_NUM (P_WD_CH_NUM ),
.P_WD_FMT (P_WD_FMT ),
.P_WD_WL (P_WD_WL )) ast_dai_ser_in_checkers (bclk, wclk, rst_an, wclk_period, bclk_period,
serial_data, sdatout_oe, frame_sync, active_clk,
active_dai, tdm_en, bclk_pol, wclk_pol, dai_en,
tdm_ch_en, ch_num, format, offset, wl, parallel_data);
bind dai_if :dai_ser_ovif dai_ser_out_checkers #(.P_WD_DATA (P_WD_DATA ),
.P_CH_NUM_MAX (P_CH_NUM_MAX ),
.P_WD_OFFSET (P_WD_OFFSET ),
.P_WD_CH_NUM (P_WD_CH_NUM ),
.P_WD_FMT (P_WD_FMT ),
.P_WD_WL (P_WD_WL )) ast_dai_ser_out_checkers (bclk, wclk, rst_an, wclk_period, bclk_period,
serial_data, sdatout_oe, frame_sync, active_clk,
active_dai, tdm_en, bclk_pol, wclk_pol, dai_en,
tdm_ch_en, ch_num, format, offset, wl, parallel_data);
bind dai_if :dai_par_ivif dai_par_in_checkers #(.P_WD_DATA (P_WD_DATA ),
.P_CH_NUM_MAX (P_CH_NUM_MAX ),
.P_WD_OFFSET (P_WD_OFFSET ),
.P_WD_CH_NUM (P_WD_CH_NUM ),
.P_WD_FMT (P_WD_FMT ),
.P_WD_WL (P_WD_WL )) ast_dai_par_in_checkers (bclk, wclk, rst_an, wclk_period, bclk_period,
serial_data, sdatout_oe, frame_sync, active_clk,
active_dai, tdm_en, bclk_pol, wclk_pol, dai_en,
tdm_ch_en, ch_num, format, offset, wl, parallel_data);
bind dai_if :dai_par_ovif dai_par_out_checkers #(.P_WD_DATA (P_WD_DATA ),
.P_CH_NUM_MAX (P_CH_NUM_MAX ),
.P_WD_OFFSET (P_WD_OFFSET ),
.P_WD_CH_NUM (P_WD_CH_NUM ),
.P_WD_FMT (P_WD_FMT ),
.P_WD_WL (P_WD_WL )) ast_dai_par_out_checkers (bclk, wclk, rst_an, wclk_period, bclk_period,
serial_data, sdatout_oe, frame_sync, active_clk,
active_dai, tdm_en, bclk_pol, wclk_pol, dai_en,
tdm_ch_en, ch_num, format, offset, wl, parallel_data);
`
我收到的错误指向我在配置数据库中设置接口的行，如下所示：
uvm_config_db#(virtual dai_if)::set(uvm_root::get(), "uvm_test_top.dai_env.dai_ag_in[0]*", "dai_vif", dai_ser_ivif);
|
ncelab: *E,TYCMPAT (/.../dai_top.sv,178|122): formal and actual do not have assignment compatible data types (expecting datatype compatible with 'virtual interface dai_if#(.P_WD_DATA(24),.P_WD_OFFSET(11),.P_CH_NUM_MAX(8),.P_WD_CH_NUM(3),.P_WD_FMT(2),.P_WD_WL(2))' but found an incompatible 'dai_if#(.P_WD_DATA(24),.P_WD_OFFSET(11),.P_CH_NUM_MAX(8),.P_WD_CH_NUM(3),.P_WD_FMT(2),.P_WD_WL(2)) instance' instead).
uvm_config_db#(virtual dai_if)::set(uvm_root::get(), "uvm_test_top.dai_env.dai_ag_in[1]*", "dai_vif", dai_par_ivif);
|
ncelab: *E,TYCMPAT (/.../dai_top.sv,179|122): formal and actual do not have assignment compatible data types (expecting datatype compatible with 'virtual interface dai_if#(.P_WD_DATA(24),.P_WD_OFFSET(11),.P_CH_NUM_MAX(8),.P_WD_CH_NUM(3),.P_WD_FMT(2),.P_WD_WL(2))' but found an incompatible 'dai_if#(.P_WD_DATA(24),.P_WD_OFFSET(11),.P_CH_NUM_MAX(8),.P_WD_CH_NUM(3),.P_WD_FMT(2),.P_WD_WL(2)) instance' instead).
uvm_config_db#(virtual dai_if)::set(uvm_root::get(), "uvm_test_top.dai_env.dai_ag_out[0]*", "dai_vif", dai_par_ovif);
|
ncelab: *E,TYCMPAT (/.../dai_top.sv,180|122): formal and actual do not have assignment compatible data types (expecting datatype compatible with 'virtual interface dai_if#(.P_WD_DATA(24),.P_WD_OFFSET(11),.P_CH_NUM_MAX(8),.P_WD_CH_NUM(3),.P_WD_FMT(2),.P_WD_WL(2))' but found an incompatible 'dai_if#(.P_WD_DATA(24),.P_WD_OFFSET(11),.P_CH_NUM_MAX(8),.P_WD_CH_NUM(3),.P_WD_FMT(2),.P_WD_WL(2)) instance' instead).
uvm_config_db#(virtual dai_if)::set(uvm_root::get(), "uvm_test_top.dai_env.dai_sb[0]*", "dai_vif", dai_ser_ivif);
|
ncelab: *E,TYCMPAT (/.../dai_top.sv,184|118): formal and actual do not have assignment compatible data types (expecting datatype compatible with 'virtual interface dai_if#(.P_WD_DATA(24),.P_WD_OFFSET(11),.P_CH_NUM_MAX(8),.P_WD_CH_NUM(3),.P_WD_FMT(2),.P_WD_WL(2))' but found an incompatible 'dai_if#(.P_WD_DATA(24),.P_WD_OFFSET(11),.P_CH_NUM_MAX(8),.P_WD_CH_NUM(3),.P_WD_FMT(2),.P_WD_WL(2)) instance' instead).
uvm_config_db#(virtual dai_if)::set(uvm_root::get(), "uvm_test_top.dai_env.dai_sb[1]*", "dai_vif", dai_ser_ivif);
|
ncelab: *E,TYCMPAT (/.../dai_top.sv,185|118): formal and actual do not have assignment compatible data types (expecting datatype compatible with 'virtual interface dai_if#(.P_WD_DATA(24),.P_WD_OFFSET(11),.P_CH_NUM_MAX(8),.P_WD_CH_NUM(3),.P_WD_FMT(2),.P_WD_WL(2))' but found an incompatible 'dai_if#(.P_WD_DATA(24),.P_WD_OFFSET(11),.P_CH_NUM_MAX(8),.P_WD_CH_NUM(3),.P_WD_FMT(2),.P_WD_WL(2)) instance' instead).
我在格式化错误消息时遇到了一些问题。指针'|'应该在每个接口实例下方，例如 dai_ser_ivif。如果我删除绑定语句，模拟运行良好，没有与上述类似的错误。所以我认为这个问题与绑定过程有关，但是，错误似乎是在抱怨我在配置数据库中使用接口（不是虚拟接口）设置虚拟接口这一事实？
非常感谢任何建议或指示。
谢谢。
【问题讨论】：
-
听起来是工具问题。
-
nchelp ncelab TYCMPAT除了告诉我错误与数据类型不匹配有关外，没有提供太多额外信息。顺便说一句，我运行了一些额外的测试并注意到如果我为代码编译的所有四个接口绑定相同的接口（例如 dai_ser_in_checkers）和相同的实例名称（例如 ast_dai_ser_in_checkers）。但是，每当我更改这些值中的任何一个时，都会得到相同的错误。关于为什么会这样的任何想法？ -
模拟器可能会统一接口，因为绑定会为每个实例创建不同的层次结构。也许您可以将 dai_ser/par_in/out_checkers 放入单个模块，并通过使用带有分层路径的
uvm_re_match或uvm_glob_to_re来做出运行时决定应该使用哪种 ser/par_in/out 模式。示例：uvm_re_match("dai_par_ivif", $sformatf("%m)) -
@Greg，您能否提供更多关于我应该在层次结构中的哪个位置使用此命令的信息？我在网上查找了一些这种用法的示例，但找不到任何东西。
标签： system-verilog uvm