Verilog 事件控制语句

Question

我目前有此代码（如下）用于 fpga 上的按钮的去抖动器，但是我收到一条错误消息，提示“在这种情况下，不支持一个始终/初始进程块中的多个事件控制语句。”每当我尝试合成设计时。导致问题的行是@(posedge clk)，但我想知道如何准确地替换这个逻辑。我本质上需要的是always @ (quarter & posedge clk)作为第一个始终阻止的敏感度列表，但这也不起作用。我对这门语言还很陌生，所以我还在研究一些语法问题。代码片段如下：

always @(quarter)
        begin

            @(posedge clk)
             begin
                 if (quarter != new) begin new <= quarter; count <= 0; end
                 else if (count == DELAY) cleanq <= new;
                 else count <= count+1;
              end
          end

Answer 1

而不是总是

@(posedge event1)         
@(posedge event2)
create aflag (1bit reg) event2done :   reg event2done; initial event2done=0;
always@(posedge event1)
begin       if (!event2done & event 2)
        // event2done=1; + type ur code 
            else if(event2done & !event 2)
                event2done =0;  end

Answer 2

伪代码：

always@(something1)
           @(something2)
                 do something

查看 cmets 以了解为什么无法合成的解释

always @(posedge clk)
             /* over here you'll have to set the default values
                for everything that's being changed in this always block, 
                you'll otherwise generate latches. Which is likely
                not what you want */
             begin
                 if (quarter != new) begin new <= quarter; count <= 0; end
                 else if (count == DELAY) cleanq <= new;
                 else count <= count+1;
              end

我目前无法访问我的 verilog 设备，因此无法确认语法正确性