VHDL实体定义答案

【问题标题】：VHDL entity definitionVHDL实体定义
【发布时间】：2020-05-25 22:49:34
【问题描述】：

我使用互联网上的一些资源来学习处理器和主板设计，我遇到了错误：VHDL: Syntax error near end。我对此很陌生，似乎无法指出错误。任何帮助将不胜感激。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ROM is
port (
    ADDR : in std_logic_vector (31 downto 0);
    D_IN : in std_logic_vector (63 downto 0);
    D_OUT : out std_logic_vector (63 downto 0);
    CLK : in std_logic;
    WE : in std_logic;
    EN : out std_logic
)
end ROM;

architecture rom_arch of ROM is

    constant INVALID_DATA : std_logic_vector (63 downto 0) := (others => 'X');
    subtype DATA_ROM_WORD is std_logic_vector (63 downto 0);
    type DATA_ROM_TABLE is array (0 to (2**3)-1) of DATA_ROM_WORD;
    signal DATA_ROM : DATA_ROM_TABLE := DATA_ROM_TABLE'
    ( 
        DATA_ROM_WORD'("0000000000000000000000000000000000000000000000000000000000000000"), --NOP
        DATA_ROM_WORD'("0000000000000000000000000000000000000000000000000000000000000000"), --NOP
        DATA_ROM_WORD'("0000000000000000000000000000000000000000000000000000000000000000"), --NOP
        DATA_ROM_WORD'("0000000000000000000000000000000000000000000000000000000000000000"), --NOP
        DATA_ROM_WORD'("0000000000000000000000000000000000000000000000000000000000000000"), --NOP
        DATA_ROM_WORD'("0000000000000000000000000000000000000000000000000000000000000000"), --NOP
        DATA_ROM_WORD'("0000000000000000000000000000000000000000000000000000000000000000"), --NOP
        DATA_ROM_WORD'("0000000000000000000000000000000000000000000000000000000000000000") --NOP
    );

begin

    process ( ADDR, CLK, WE ) is
    begin
        if ADDR <= X"FF" and CLK = '1'
        then
            EN <= '1';
            D_OUT <= DATA_ROM(conv_integer(ADDR));
            if WE='1'
            then
                DATA_ROM(conv_integer(ADDR)) <= D_IN;
            end if;
            EN <= '0';
        end if;
    end process;

end rom_arch;

【问题讨论】：

一些工具更擅长指出印刷错误 - ghdl -a rom.vhdl rom.vhdl:13:2:error: missing ";" at end of port clause ghdl:error: compilation error。如果您在 Minimal 下阅读了How to create a Minimal, Reproducible Example，那么您可以在提出问题之前实施两条建议。只需要实体声明。那些 NOP 表达式可能是 DATA_ROM_WORD'(others => '0')（使用聚合更短）。

标签： vhdl xilinx-ise

【解决方案1】：

结束前缺少分号。始终检查该标点符号。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ROM is
port (
    ADDR : in std_logic_vector (31 downto 0);
    D_IN : in std_logic_vector (63 downto 0);
    D_OUT : out std_logic_vector (63 downto 0);
    CLK : in std_logic;
    WE : in std_logic;
    EN : out std_logic
);
end ROM;

architecture rom_arch of ROM is

    constant INVALID_DATA : std_logic_vector (63 downto 0) := (others => 'X');
    subtype DATA_ROM_WORD is std_logic_vector (63 downto 0);
    type DATA_ROM_TABLE is array (0 to (2**3)-1) of DATA_ROM_WORD;
    signal DATA_ROM : DATA_ROM_TABLE := DATA_ROM_TABLE'
    ( 
        DATA_ROM_WORD'("0000000000000000000000000000000000000000000000000000000000000000"), --NOP
        DATA_ROM_WORD'("0000000000000000000000000000000000000000000000000000000000000000"), --NOP
        DATA_ROM_WORD'("0000000000000000000000000000000000000000000000000000000000000000"), --NOP
        DATA_ROM_WORD'("0000000000000000000000000000000000000000000000000000000000000000"), --NOP
        DATA_ROM_WORD'("0000000000000000000000000000000000000000000000000000000000000000"), --NOP
        DATA_ROM_WORD'("0000000000000000000000000000000000000000000000000000000000000000"), --NOP
        DATA_ROM_WORD'("0000000000000000000000000000000000000000000000000000000000000000"), --NOP
        DATA_ROM_WORD'("0000000000000000000000000000000000000000000000000000000000000000") --NOP
    );

begin

    process ( ADDR, CLK, WE ) is
    begin
        if ADDR <= X"FF" and CLK = '1'
        then
            EN <= '1';
            D_OUT <= DATA_ROM(conv_integer(ADDR));
            if WE='1'
            then
                DATA_ROM(conv_integer(ADDR)) <= D_IN;
            end if;
            EN <= '0';
        end if;
    end process;

end rom_arch;

【讨论】：