Verilog 模块输出 reg 驱动输出 reg？

Question

所以我试图在一个模块中实例化一个模块。根模块具有驱动输出引脚的输出端口，我希望内部模块直接驱动这些端口，但我无法让它正常工作。

/*
A root module for the 005_135-scanner_mainboard_revA_sch-pcb. Can be used as a test bench for testing peripheral devices but has been designed to be the master root module for the final code.
All IO is included and reset pins on peripheral devices driven active reset with data lines driven to an appropriate value (located in the ‘initial block’).
George Waller. 09/08/15.
*/

module root_module( ft_reset, ft_usb_prsnt, ft_bus_pwrsav, ft_bus_oe,             ft_bus_clkout, ft_bus_siwu, ft_bus_wr, ft_bus_rd, ft_bus_rxf, ft_bus_txe, ft_bus_d,
                        mtr_fault, mtr_config, mtr_m1, mtr_m0, mtr_rst, mtr_out_en, mtr_step, mtr_dir,
                        ccd_driver_oe, ccd_p1, ccd_p2, ccd_cp, ccd_rs, ccd_sh,
                        dac1_sdin, dac1_sclk, dac1_sync, dac2_sdin, dac2_sclk, dac2_sync,
                        adc_pwrdn, adc_encode, adc_d,
                        fpga_reset,
                        clk,
                        gpio,
                        led_ctrl,
                        leds);

//Input declarations
input wire          ft_usb_prsnt, ft_bus_clkout, ft_bus_rxf, ft_bus_txe,
                        mtr_fault, 
                        fpga_reset,
                        clk;

input wire [7:0]    adc_d;

//Output declarations
output reg          ft_reset, ft_bus_pwrsav, ft_bus_oe, ft_bus_siwu, ft_bus_wr, ft_bus_rd,
                        mtr_config, mtr_m1, mtr_m0, mtr_rst, mtr_out_en, mtr_step, mtr_dir,
                        ccd_driver_oe, ccd_p1, ccd_p2, ccd_cp, ccd_rs, ccd_sh,
                        adc_pwrdn, adc_encode,
                        led_ctrl;

output reg          dac1_sdin, dac1_sclk, dac1_sync, dac2_sdin, dac2_sclk, dac2_sync;

output reg [7:0]    leds;

//Input output declarations.
inout reg  [7:0]    ft_bus_d;

inout reg [16:0]    gpio;

//Variables go here     

integer count, count1, state, pixel_n, line_n, t_int;   
integer data[8];

reg en;

//Initial values on start up.
initial
begin
    //IO initial setup values.
    ft_reset = 1; ft_bus_pwrsav = 1; ft_bus_oe = 1; ft_bus_siwu = 0; ft_bus_wr = 1; ft_bus_rd = 1;  //NEED TO APPLY REAL VAULES!!!
    mtr_config = 1; mtr_m1 = 1; mtr_m0 = 1; mtr_rst = 1; mtr_out_en = 1; mtr_step = 0; mtr_dir = 0;
    ccd_driver_oe = 1; ccd_p1 = 0; ccd_p2 = 0; ccd_cp = 0; ccd_rs = 0; ccd_sh = 0;
    dac1_sdin = 0; dac1_sclk = 0; dac1_sync = 0; dac2_sdin = 0; dac2_sclk = 0; dac2_sync = 0;
    adc_pwrdn = 0; adc_encode = 0;
    led_ctrl = 0;
    leds = 0;
    gpio = 0;
    ft_bus_d = 0;

    //Variables setup values.   
    count = 0;
    count1 = 0;
    state = 0;
    pixel_n = 0;
    line_n = 0;
    t_int = 10000;  //t_int = integration time. integration time (seconds) =                  t_int * 10x10^-9. 
end //End initial

//Some other code goes here.
always @(posedge ft_bus_clkout)
begin
    if(count == 50000000)
        begin
            en <= 1;
            count = 0;
        end
        else
        begin
            en <= 0;
            count = count + 1;
    end 
end //End always

AD5601_module AD5601(.en(en), .clk(clk), .data(127),.sdout(dac1_sdin),
.sclk(dac1_sclk), .sync(dac1_sync));    

endmodule   //End module. 

还有内部模块：

module AD5601_module(en, clk, data, sdout, sclk, sync);

        input wire          clk;
        input wire          en;
        input wire [7:0]    data;

        output reg          sdout, sclk, sync;

        integer sclk_count;
        integer data_state;
        integer delay_counter;
        integer pd[2];

        initial
        begin
            sclk_count = 0;
            data_state = 99;
            delay_counter = 0;
            pd[0] = 0;
            pd[1] = 0;

            sdout = 0;
            sclk = 0;
            sync = 1;
        end

        always @ (posedge en)
        begin
            if(data_state == 99)data_state <= 0;
        end


        always @ (posedge clk)
        begin
            if(sclk_count == 49)
            begin
                sclk_count = 0;
                sclk = ~sclk;
            end
            else sclk_count = sclk_count + 1;

        end

        always @ (posedge sclk)
        begin
            case(data_state)
                0:  begin
                    sync = 0;
                    sdout <= pd[1];
                    data_state <= 1;
                end

                1:  begin
                    sdout <= pd[0];
                    data_state <= 2;
                end             

                2:  begin
                    sdout <= data[7];
                    data_state <= 3;
                end             

                3:  begin
                    sdout <= data[6];
                    data_state <= 4;
                end             

                4:  begin
                    sdout <= data[5];
                    data_state <= 5;
                end             

                5:  begin
                    sdout <= data[4];
                    data_state <= 6;
                end             

                6:  begin
                    sdout <= data[3];
                    data_state <= 7;
                end             

                7:  begin
                    sdout <= data[2];
                    data_state <= 8;
                end             
                8:  begin
                    sdout <= data[1];
                    data_state <= 9;
                end             

                10:begin
                    sdout <= 0;
                    if(delay_counter == 6)                          
                    begin
                        data_state <= 99;
                        delay_counter <= 0;
                        sync = 1;
                    end
                    else delay_counter = delay_counter + 1;
                end             
            endcase
        end
endmodule

所以我得到了错误的代码

'输出或输入端口应连接到结构网络 表达'

.

如果我将根模块或内部模块中的输出更改为连线，则会收到错误消息“左侧的表达式应为变量类型”。

所以现在我不知道你是如何嵌套输出的！一些帮助将不胜感激！

谢谢

Answer 1

inout 端口应该是网络类型（wire 或 tri）而不是 reg。 reg 没有冲突解决（当有两个或更多活动驱动程序时）。不应在程序块中分配 inout（例如 always-block、initial-block）。它应该是一个简单的assign 声明，如下所示。设计人员必须确保在任何时候 IO 上只有活动驱动程序。

assign io_port_name = driver_enable ? io_out_value : 'bz; // io_out_value should be a flop

只有在当前模块内的程序块（例如always-block、initial-block）中分配输出时，才应将其声明为output reg。所有其他输出应为output 或output wire（这些标识符是同义词；前者是隐式的，而后者是显式的）。只能在一个always 内分配一个。 FPGA 允许initial 块，ASIC/IC 不允许。

如果启用了 SystemVerilog，请将 output reg 替换为 output logic。 logic 可用于触发器和单向网络。 logic 不推荐用于inout； logic 像 reg 没有冲突解决。

数组integer data[8]; 和integer pd[2]; 是SystemVerilog 语法，与Verilog 不兼容。启用 SystemVerilog 或更改为 integer data[0:7]; 和 integer pd[0:1];
通过将文件扩展名从.v更改为.sv，可以为每个文件启用SystemVerilog；推荐的。模拟器/合成器通常有一个开关来强制所有 Verilog 被视为 SystemVerilog；不推荐，如果想走这条路线，请参阅模拟器/合成器手册。