在 VHDL 结构中连接组件

Question

我正在使用 VHDL，尝试连接三个组件 M88、A8、A16，但是一旦我合成了电路并查看 RTL 原理图，就没有连接任何组件。例如，我想将 M88 'out_high' 的输出连接到组件 A16 的输入 A16。我通过定义一个信号 OUT_H 来做到这一点。下面是主电路的结构和M88和A16的实体。库“Mult8x8.Components”是我定义组件的地方。我定义的组件之间的任何连接都不起作用，但我相信我正在犯同样的错误，我无法弄清楚。

谢谢

entity Structure is
Port ( 
       Clock, RST, Start : in  BIT;
          IN1, IN2 : in  BIT_VECTOR (7 downto 0);
       RESULT8x8 : out  BIT_VECTOR (15 downto 0);
          Done : out BIT_VECTOR(3 downto 0)
      );
end Structure;

architecture Structural of Structure is use work.Mult8x8_Components.all;
signal OUT_M1, OUT_M2: BIT_VECTOR(7 downto 0);
signal OUT_H, OUT_L, ADD_MIXout, result16: BIT_VECTOR(15 downto 0);
signal Zero, Init, Shift, Add, Low: BIT := '0'; 
signal High: BIT := '1';
signal F, OFL, REGclr: BIT;
signal DD : BIT_VECTOR(3 downto 0);

begin
--  REGclr <= Init or RST;
    RESULT8x8 <= result16;
    Done <= DD;
    M88 : Mult8x8 port map 
        (CLK => Clock, RESET => RST, Start => Start, input1 => IN1, input2 => IN2, out_high => OUT_H, out_low => OUT_L, out_mix1 => OUT_M1, out_mix2 => OUT_M2, DONE => DD );
    A8 : Adder8 port map (A=>OUT_M1, B=>OUT_M2, Cin=>Low, Cout=>OFL, Sum=>ADD_MIXout(11 downto 4));
    A16 : Adder16 port map (A16=> OUT_H, B16 => OUT_L, E16 => ADD_MIXout, Cin16 => low, Cout16 => OFL, Sum16 => result16 );
end Structural;







entity Mult8x8 is
    Port( 
             CLK, RESET, Start : in BIT;
             input1 : in  BIT_VECTOR (7 downto 0);
          input2 : in  BIT_VECTOR (7 downto 0);
          out_high : out BIT_VECTOR (15 downto 0) := (others =>'0');
             out_low : out BIT_VECTOR (15 downto 0) := (others =>'0');
             out_mix1 : out BIT_VECTOR (7 downto 0) := (others =>'0');
             out_mix2 : out BIT_VECTOR (7 downto 0) := (others =>'0');
             DONE : out BIT_VECTOR (3 downto 0)
             );
end Mult8x8;




entity Adder16 is
    Port ( A16, B16, E16 : in BIT_VECTOR (15 downto 0);
           Cin16 : in BIT;
              Cout16 : out BIT;
           Sum16 : out BIT_VECTOR (15 downto 0));
end Adder16;

Answer 1

当您想在一个上层实体中映射多个实体（就像您在那里所做的那样）时，您需要首先在一个单独的文件中定义这些实体（我以为您会这样做）。然后，我建议，在“顶层”（您的实体结构）中，您需要在架构的 begin 术语之前使用不同的术语来实例化它们：component。

注意：显然，这只有在子实体编译在同一个工作库中时才有效。

这是一个如何更改代码的示例。请注意，您缺少需要像其他两个一样定义的组件 Adder8。

use work.Mult8x8_Components.all;

entity Structure is
Port ( 
       Clock, RST, Start : in  BIT;
       IN1, IN2 : in  BIT_VECTOR (7 downto 0);
       RESULT8x8 : out  BIT_VECTOR (15 downto 0);
       Done : out BIT_VECTOR(3 downto 0)
      );
end Structure;

architecture Structural of Structure is 
signal OUT_M1, OUT_M2: BIT_VECTOR(7 downto 0);
signal OUT_H, OUT_L, ADD_MIXout, result16: BIT_VECTOR(15 downto 0);
signal Zero, Init, Shift, Add, Low: BIT := '0'; 
signal High: BIT := '1';
signal F, OFL, REGclr: BIT;
signal DD : BIT_VECTOR(3 downto 0);

component Mult8x8 is
    Port( 
          CLK, RESET, Start : in BIT;
          input1 : in  BIT_VECTOR (7 downto 0);
          input2 : in  BIT_VECTOR (7 downto 0);
          out_high : out BIT_VECTOR (15 downto 0) := (others =>'0');
          out_low : out BIT_VECTOR (15 downto 0) := (others =>'0');
          out_mix1 : out BIT_VECTOR (7 downto 0) := (others =>'0');
          out_mix2 : out BIT_VECTOR (7 downto 0) := (others =>'0');
          DONE : out BIT_VECTOR (3 downto 0)
        );
end component ;

component Adder16 is
    Port ( 
           A16, B16, E16 : in BIT_VECTOR (15 downto 0);
           Cin16 : in BIT;
           Cout16 : out BIT;
           Sum16 : out BIT_VECTOR (15 downto 0)
         );
end component ;

begin

--  REGclr <= Init or RST;
    RESULT8x8 <= result16;
    Done <= DD;

    M88 : Mult8x8 port map 
        (CLK => Clock, 
         RESET => RST, 
         Start => Start, 
         input1 => IN1, 
         input2 => IN2, 
         out_high => OUT_H, 
         out_low => OUT_L, 
         out_mix1 => OUT_M1, 
         out_mix2 => OUT_M2, 
         DONE => DD );

    A8 : Adder8 port map 
         (A=>OUT_M1, 
         B=>OUT_M2, 
         Cin=>Low, 
         Cout=>OFL, 
         Sum=>ADD_MIXout(11 downto 4));

    A16 : Adder16 port map 
        (A16=> OUT_H, 
         B16 => OUT_L, 
         E16 => ADD_MIXout, 
         Cin16 => low, 
         Cout16 => OFL, 
         Sum16 => result16 );

end Structural;

另一种在不调用组件的情况下实例化实体的方法如下：

A8: entity work.adder8 port map (OUT_M1, OUT_M2, Low, OFL, ADD_MIXout(11 downto 4));

在这种情况下，您不需要指定端口，它们是按照实体中定义的顺序获取的。