verilog, FSM, 有限状态机, 错误答案

【问题标题】：verilog, FSM, finite state machine ,errorverilog, FSM, 有限状态机, 错误
【发布时间】：2015-10-14 20:47:25
【问题描述】：

当我在 Modelsim 中模拟以下模块时，我没有看到 cikis 的任何输出波形，请告诉我这个 FSM 和测试台出了什么问题。

我的模块有 3 个输入和 1 个输出。

    module sayici_fsm( clock, reset,cikis, out);

    input  wire clock;
    input  wire reset;

    output reg  [2:0] cikis;
    output wire       out;

    localparam durum0 = 3'd0,
               durum1 = 3'd1,
               durum2 = 3'd2,
               durum3 = 3'd3,
               durum4 = 3'd4,
               durum5 = 3'd5,
               durum6 = 3'd6,
               durum7 = 3'd7;

    reg [2:0] currentstate;
    reg [2:0] nextstate;

    assign out = (durum1& durum3);

    always @(*) begin
        cikis = 3'b000;
        case (currentstate)
            durum0: 
            begin
                 cikis = 3'b000;
            end
            durum1: 
            begin
                cikis = 3'b000;
            end
            durum2: 
            begin
                cikis = 3'b010;
            end
            durum3: 
            begin
                cikis = 3'b100;
            end
            durum4: 
            begin
                cikis = 3'b110;
            end
        endcase
    end

  always @(posedge clock)  begin
    if(reset)  currentstate <= durum0 ;
    else       currentstate <= nextstate;
    end

  always @(*) begin
    nextstate =currentstate;
      case (currentstate)
        durum0: 
          begin
            nextstate = durum1;
          end
        durum1: 
          begin
            nextstate = durum2;
          end
        durum2: 
          begin
            nextstate = durum3;
          end
        durum3: 
          begin
            nextstate = durum4;
          end
         durum4: 
           begin
             nextstate = durum1;
           end
         durum5: 
           begin
             nextstate = durum0;
           end
         durum6: 
           begin
             nextstate = durum0;
           end
          durum7: 
            begin
              nextstate = durum0;
            end
        endcase
    end    
    endmodule

module sayici_fsm_tb();

wire [2:0] cikis;
wire       out;

reg clock;    
reg reset;    

sayici_fsm u1(.out   (out  ),
              .clock (clock),
              .cikis (cikis),
              .reset (reset)
             );

initial 
begin
    $display( $time,  "Similasyon Baslasin");
    $display( " Time  clock reset  enable giris cikis");
    $monitor ("time =%d, clock =%b, reset=%b, cikis=%b  out =%b", $time, clock, reset, cikis,out);

    reset = 1'b1;
    clock = 1'b0;
#5  reset = 1'b0;
    clock = 1'b1;
#100 $finish;  
end

always #7  clock =!clock;

endmodule

【问题讨论】：

你在modelsim波形中看到时钟了吗？

标签： verilog fsm state-machine

【解决方案1】：

错误是在测试台中生成重置，因为未正确初始化cikis 变为默认值'x'

     reset = 1'b1;
     clock = 1'b0;
  #5 reset = 1'b0;  // give more time  so that at posedge of clk reset is asserted say #8
     clock = 1'b1;  // remove from tb
  #100 $finish;  
end
always #7  clock =!clock;

从上面的 sn-p 中，复位在 5 ns 时变为低电平，但时钟在 7 ns 处获得第一个 posedge，在时钟的 posedge 期间，当前状态被编码以获得 durum0 的值，如下所述

always @(posedge clock)  begin
if(reset)  currentstate <= durum0 ;
else       currentstate <= nextstate;
end

要解决错误，请等待相当多的时钟并重置总线。

【讨论】：