#interrupt-cells 是 2 但中断是 3 元组答案

【问题标题】：#interrupt-cells is 2 but interrupts is a 3-tuple#interrupt-cells 是 2 但中断是 3 元组
【发布时间】：2019-01-10 14:34:52
【问题描述】：

我正在查看 Beagle Bone Black 的设备树，并从 am57xx-beagle-x15.dts 开始。深入到dra7.dtsi 我发现gpio1：

gpio1: gpio@4ae10000 {
            compatible = "ti,omap4-gpio";
            reg = <0x4ae10000 0x200>;
            interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
            ti,hwmods = "gpio1";
            gpio-controller;
            #gpio-cells = <2>;
            interrupt-controller;
            #interrupt-cells = <2>;
        };

我读过#interrupt-cells 给出了interrupts 列表中的项目中预期的u32 或单元格的数量。但是当我查看interrupts 时，我看到了一个三元组：<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>。很想知道，为什么它包含 3 个细胞而不是 2 个？

【问题讨论】：

请注意，am57xx-beagle-x15.dts 不是与 BBB 相关的文件。这是为 BeagleBoard X15 准备的！
@TBR - 谢谢！好吧，我什至没有找对地方:'(虽然仍然对中断单元的数量感到困惑....

标签： linux beagleboneblack beagleboard

【解决方案1】：

这是一个很晚的答案，但添加一个以便有人可以得到帮助。
我无法从我当前的 linux 5.15 源代码中找到确切的 dts 文件。但是节点的中断父节点应该需要 3 个单元格作为中断属性。对于 gic，通常它需要 3 个值 - {中断类型、中断号、标志}。在gic的设备绑定文档中（Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml in linux 5.15）

  "#interrupt-cells":
    const: 3
    description: |
      The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
      interrupts.

      The 2nd cell contains the interrupt number for the interrupt type.
      SPI interrupts are in the range [0-987].  PPI interrupts are in the
      range [0-15].

      The 3rd cell is the flags, encoded as follows:
        bits[3:0] trigger type and level flags.
          1 = low-to-high edge triggered
          2 = high-to-low edge triggered (invalid for SPIs)
          4 = active high level-sensitive
          8 = active low level-sensitive (invalid for SPIs).
        bits[15:8] PPI interrupt cpu mask.  Each bit corresponds to each of
        the 8 possible cpus attached to the GIC.  A bit set to '1' indicated
        the interrupt is wired to that CPU.  Only valid for PPI interrupts.
        Also note that the configurability of PPI interrupts is IMPLEMENTATION
        DEFINED and as such not guaranteed to be present (most SoC available
        in 2014 seem to ignore the setting of this flag and use the hardware
        default value).

【讨论】：