常见 17-165 解析时位置选项过多答案

【问题标题】：Common 17-165 Too many positional options when parsing常见 17-165 解析时位置选项过多
【发布时间】：2022-10-08 09:06:11
【问题描述】：

我试图让我的 BASYS 3 板 (xc7a35tcpg236-1) 通过开关接受 4 位输入，并在 7 段显示器上显示相应的十六进制字符。

但是，我不断收到以下错误，“[Common 17-165] 解析'255/ECE255Lab5-2/ECE255Lab5-2.srcs/utils_1/imports/synth_1/Display.dcp'时位置选项太多，请输入' read_checkpoint -help' 获取使用信息。”

我不知道如何解决这个问题，也找不到解决方案，因此我们将不胜感激。

高密度脂蛋白：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
entity Display is
Port ( --clk : in STD_LOGIC;-- 100Mhz clock on Basys 3 FPGA board
Anode_Activate : out STD_LOGIC_VECTOR (3 downto 0);-- 4 Anode signals
LED_out : out STD_LOGIC_VECTOR (6 downto 0);-- Cathode patterns of 7-segment display
sw : in STD_logic_vector(3 downto 0));
end Display;
architecture Behavioral of Display is
begin
process(sw)
begin
anode_activate <= "0000";
case sw is
when "0000" => LED_out <= "0000001"; -- "0"
when "0001" => LED_out <= "1001111"; -- "1"
when "0010" => LED_out <= "0010010"; -- "2"
when "0011" => LED_out <= "0000110"; -- "3"
when "0100" => LED_out <= "1001100"; -- "4"
when "0101" => LED_out <= "0100100"; -- "5"
when "0110" => LED_out <= "0100000"; -- "6"
when "0111" => LED_out <= "0001111"; -- "7"
when "1000" => LED_out <= "0000000"; -- "8"
when "1001" => LED_out <= "0000100"; -- "9"
when "1010" => LED_out <= "0000010"; -- a
when "1011" => LED_out <= "1100000"; -- b
when "1100" => LED_out <= "0110001"; -- C
when "1101" => LED_out <= "1000010"; -- d
when "1110" => LED_out <= "0110000"; -- E
when "1111" => LED_out <= "0111000"; -- F
when others => NULL;
end case;
end process;
end Behavioral;

XDC：

set_property PACKAGE_PIN W4 [get_ports {Anode_Activate[3]}]
set_property PACKAGE_PIN V4 [get_ports {Anode_Activate[2]}]
set_property PACKAGE_PIN U4 [get_ports {Anode_Activate[1]}]
set_property PACKAGE_PIN U2 [get_ports {Anode_Activate[0]}]
set_property PACKAGE_PIN W7 [get_ports {LED_out[6]}]
set_property PACKAGE_PIN W6 [get_ports {LED_out[5]}]
set_property PACKAGE_PIN U8 [get_ports {LED_out[4]}]
set_property PACKAGE_PIN V8 [get_ports {LED_out[3]}]
set_property PACKAGE_PIN U5 [get_ports {LED_out[2]}]
set_property PACKAGE_PIN V5 [get_ports {LED_out[1]}]
set_property PACKAGE_PIN U7 [get_ports {LED_out[0]}]
set_property PACKAGE_PIN W17 [get_ports {sw[3]}]
set_property PACKAGE_PIN W16 [get_ports {sw[2]}]
set_property PACKAGE_PIN V16 [get_ports {sw[1]}]
set_property PACKAGE_PIN V17 [get_ports {sw[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Anode_Activate[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Anode_Activate[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Anode_Activate[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Anode_Activate[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED_out[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED_out[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED_out[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED_out[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED_out[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED_out[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED_out[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]

【问题讨论】：

标签： vhdl fpga vivado

【解决方案1】：

该问题与 Utility 文件夹中生成的文件有关。我不知道它为什么在那里，但是在我删除了 Utility 文件夹中的所有内容后，比特流完美地生成了。

【讨论】：

我对此表示赞成，因为有几个人在同一平台上就同一问题提出了相同的问题。这是我在项目/平台/问题中看到的最干净的配置。 “删除旧文件”

【解决方案2】：

多谢兄弟！为我修好了。非常感激：）

【讨论】：