【发布时间】:2022-10-01 02:23:58
【问题描述】:
我正在尝试使用 f4pga 将 f4pga-examples 中的一个示例从 verilog 编译成比特流,并按照此处的说明在我的 ZYBO Zynq 7000 上运行它: https://f4pga-examples.readthedocs.io/en/latest/running-examples.html (请注意,我必须用 \"fatload\" 代替 \"load\",因为没有 \"load\"。)
zynq-uboot> fatload mmc 0 0x10000000 top.bit
reading top.bit
2083847 bytes read in 349 ms (5.7 MiB/s)
zynq-uboot> fpga loadb 0 0x10000000 2083847
design filename = \"/tmp/tmpoyzn0_4q;Generator=xc7frames2bit\"
fpga_loadbitstream: Wrong bitstream ID for this device
fpga_loadbitstream: Bitstream ID xc7z010clg400-1, current device ID 0/7z010
fpga - loadable FPGA image support
Usage:
fpga [operation type] [device number] [image address] [image size]
fpga operations:
dump [dev] Load device to memory buffer
info [dev] list known device information
load [dev] [address] [size] Load device from memory buffer
loadb [dev] [address] [size] Load device from bitstream buffer
(Xilinx only)
loadmk [dev] [address] Load device generated with mkimage
For loadmk operating on FIT format uImage address must include
subimage unit name in the form of addr:<subimg_uname>
zynq-uboot>
想法?是否可以像将比特流 ID 更改为其他内容一样简单?
标签: fpga