1、避免异步反馈；
2、移除竞争冒险；
3、分割大计数器；
4、利用空闲的引脚来增加内部电路节点的可控制性和可观测性（controllability and observability)；
5、使电路可以初始化到一个已知状态；
6、Use scan testing where appropriate on register elements that are clocked off the same clock;
7、Run fault simulation on areas of the circuit not covered using scan techniques. Examples includes gated clocks or possibly an asynchronous interface to a microprocessor;
8、Use test vector comparison techniques during simulation to ensure test insertion does ont alter the functionality of the design;
9、Break the scan chain into several small chains of the similar length.