一、编写verilog源文件，在diamond中编译。编写testbench文件。在diamond设置中将仿真工具设置为modelsim，运行仿真向导
二、自动进入modelsim，
编译全部
运行仿真---library的work下，选则测试文件，右键仿真
点击运行到或者运行一段等
testbench实例
1 `timescale 1 ns/ 1 ps 2 module clk_tb(); 3 // constants 4 // general purpose registers 5 reg eachvec; 6 // test vector input registers 7 reg CLK; 8 reg RSTn; 9 reg KEY_set; 10 reg KEY_add; 11 wire lcd_rst,sce,sclk,sdin,cd; 12 13 // assign statements (if any) 14 top sim 15 ( 16 .CLK(CLK), 17 .RSTn(RSTn), 18 .KEY_set(KEY_set), 19 .KEY_add(KEY_add), 20 .lcd_rst(lcd_rst), 21 .sce(sce), 22 .sclk(sclk), 23 .sdin(sdin), 24 .cd(cd) 25 ); 26 initial 27 begin 28 CLK = 0; 29 forever #25 CLK = ~CLK; 30 end 31 32 initial 33 begin 34 RSTn =1; 35 #200 RSTn = 0; 36 #300 RSTn = 1; 37 end 38 39 initial 40 begin 41 KEY_set =1; 42 #1000 KEY_set =~KEY_set; 43 end 44 45 endmodule
1 /************************************************** 2 module: DDS_test 3 author: wanganran 4 description: The testbench for module DDS 5 input: 6 output: 7 date: 2015.11.05 8 **************************************************/ 9 `timescale 1ns / 100ps 10 11 module DDS_test; 12 13 parameter CLK_PERIOD = 40; //CLK_PERIOD=40ns, Frequency=25MHz 14 15 reg sys_clk; 16 initial 17 sys_clk = 1'b0; 18 always 19 sys_clk = #(CLK_PERIOD/2) ~sys_clk; 20 21 reg sys_rst_n; //active low 22 initial 23 begin 24 sys_rst_n = 1'b0; 25 #200; 26 sys_rst_n = 1'b1; 27 end 28 29 wire dac_clk_out; 30 wire [9:0] dac_data_out; 31 DDS DDS_uut 32 ( 33 .clk_in(sys_clk), //clock in 34 .rst_n_in(sys_rst_n), //reset, active low 35 .dds_en_in(1), //dds work enable 36 .f_increment(24'h10000), //frequency increment 37 .p_increment(0), //phase increment 38 .dac_clk_out(dac_clk_out), //clock out 39 .dac_data_out(dac_data_out) //data out 40 ); 41 42 endmodule