This application note is written for logic designers who are new to HDL verification flows, and who do not have extensive testbench-writing experience.
![[文档]. Xilinx - 编写有效的Testbenches](http://images.cnblogs.com/likecs_com/yuphone/WindowsLiveWriter/757a4c84089b.XilinxTestbenches_A018/image_2.png "[文档]. Xilinx - 编写有效的Testbenches")
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This application note is written for logic designers who are new to HDL verification flows, and who do not have extensive testbench-writing experience.
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