Abstract
無法在SignalTap II觀察reg與wire，主要都是因為被Quartus II優化的關係，在Quartus II簡單的設定，就能增加SignalTap II能觀察的數量。
Introduction
使用環境：Quartus II 8.0
在(原創) 如何使用SignalTap II觀察reg與wire值? (SOC) (Verilog) (Quartus II) (SignalTap II)中，我透過synthesis attribute強制指定Quartus II對某個reg與wire不加以優化，以方便SignalTap II觀察，雖然可行，但必須改code是其缺點，若能在Quartus II透過設定的方式，就能在SignalTap II觀察到reg與wire，是比較方便的方式。
在Using SignalTap II Embedded Logic Analyzers in SOPC Builder Systems這篇paper的p.3提到：
By turning off the Incremental Compilation option, pre-synthesis signals can be added to the SignalTap II ELA in the later sections. Pre-synthesis signals exist after design elaboration but before any synthisis optimations are done. This set of signals should reflect your register transfer level(RTL) signals.
設定方式
Assignments -> Settings : Category : Compilation Process Settings -> Incremental Compilation
See Also
(原創) 如何使用SignalTap II觀察reg與wire值? (SOC) (Verilog) (Quartus II) (SignalTap II)
Reference
Using SignalTap II Embedded Logic Analyzers in SOPC Builder Systems